AT40K40LV-3EQC Atmel, AT40K40LV-3EQC Datasheet

IC FPGA 3.3V 2304 CELL 240PQFP

AT40K40LV-3EQC

Manufacturer Part Number
AT40K40LV-3EQC
Description
IC FPGA 3.3V 2304 CELL 240PQFP
Manufacturer
Atmel
Series
AT40K/KLVr
Datasheet

Specifications of AT40K40LV-3EQC

Number Of Logic Elements/cells
2304
Total Ram Bits
18432
Number Of I /o
193
Number Of Gates
50000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
240-BFQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Labs/clbs
-
Other names
AT40K40LV3EQC
Features
Device
Usable Gates
RowsXColumns
Cells
Registers
RAM Bits
I/O (max)
Ultra High Performance
FreeRAM
84 - 384 PCI Compliant I/Os
8 Global Clocks
Cache Logic
Pin-Compatible Package Options
Industry-Standard Design Tools
Intellectual Property Cores
Easy Migration to Atmel Gate Arrays for High Volume Production
– System Speeds to 100 MHz
– Array Multipliers > 50 MHz
– 10ns Flexible SRAM
– Internal 3-State Capability in each Cell
– Flexible, Single/Dual Port, Sync/Async 10 ns SRAM
– 2,048 - 18,432 Bits of Distributed SRAM Independent of Logic Cells
– 3V/5V Capability
– Programmable Output Drive
– Fast, Flexible Array Access Facilitates Pin-Locking
– Pin Compatible with XC4000, XC5200 FPGAs
– Fast, Low Skew Clock Distribution
– Programmable Rising/Falling Edge Transitions
– Distributed Clock Shut-Down Capability for Low Power Management
– Global Reset/Asynchronous Reset Options
– 4 Additional Dedicated PCI Clocks
– Unlimited Reprogrammability via Serial or Parallel Modes
– Enables Adaptive Designs
– Enables Fast Vector Multiplier Updates
– QuickChange
– Plastic Leaded Chip Carriers (PLCC)
– Thin, Plastic Quad Flat Packs (VQFP, TQFP, PQFP)
– Ball Grid Arrays (BGA)
– Pin Grid Arrays (PGAs)
– Seamless Integration (Libraries, Interface, Full Back-Annotation) with
– Timing Driven Placement & Routing
– Automatic/Interactive Multi-Chip Partitioning
– Fast, Efficient Synthesis
– Over 50 Automatic Component Generators Create 1000’s
– Fir Filters, UARTs, PCI, FFT and other System Level Functions
Concept, Everest, Exemplar, Mentor, OrCAD, Synario, Synopsys,
Verilog, Veribest, Viewlogic, Synplicity
of Reusable, Fully Deterministic Logic and RAM Functions
®
Dynamic Full/Partial Reconfigurability In-System
Tools for Fast, Easy Design Changes
AT40K05
5K - 10K
16 x 16
2,048
256
256
128
10K - 20K
AT40K10
24 x 24
4,608
576
576
192
20K - 30K
AT40K20
32 x 32
1,024
1,024
8,192
256
40K - 50K
AT40K40
48 x 48
18,432
2,304
2,304
384
AT40K FPGAs
with FreeRAM™
AT40K05
AT40K10
AT40K20
AT40K40
AT40K
Rev. 0896B–01/99
1

Related parts for AT40K40LV-3EQC

AT40K40LV-3EQC Summary of contents

Page 1

... Over 50 Automatic Component Generators Create 1000’s of Reusable, Fully Deterministic Logic and RAM Functions • Intellectual Property Cores – Fir Filters, UARTs, PCI, FFT and other System Level Functions • Easy Migration to Atmel Gate Arrays for High Volume Production Device AT40K05 Usable Gates 5K - 10K RowsXColumns ...

Page 2

... The Atmel architecture was developed to provide the high- est levels of performance, functional density and design flexibility in an FPGA. The cells in the Atmel array are small, efficient and can implement any pair of Boolean functions of (the same) three inputs or any single Boolean function of four inputs. The cell’ ...

Page 3

... The Symmetrical Array At the heart of the Atmel architecture is a symmetrical array of identical cells (Figure 1). The array is continuous from one edge to the other, except for bus repeaters spaced every four cells (Figure 2). At the intersection of each Figure 1. Symmetrical Array Surrounded by I/O (AT40K20) repeater row and column RAM block accessible by adjacent buses ...

Page 4

Figure 2. Floorplan (representative portion) RAM RAM RAM RAM The Busing Network Figure 3 depicts one of five identical busing planes. Each plane has ...

Page 5

Figure 3. Busing Plane (one of five) = AT40K Cell = Local/Local or Express/Express Turn Point = Row Repeater = Column Repeater AT40K 5 ...

Page 6

Cell Connections Figure 4(a) depicts direct connections between a cell and its eight nearest neighbors. Figure 4(b) shows the connec- tions between a cell five horizontal local buses (one per Figure 4. Cell Connections CEL CEL CEL (a) Cell to ...

Page 7

The Cell Figure 5 depicts the AT40K cell. Configuration bits for sep- arate muxes and pass gates are independent. All permuta- tions of programmable muxes and pass gates are legal connected to the vertical local bus in plane ...

Page 8

Figure 6. Some Single Cell Modes Synthesis Mode Arithmetic Mode DSP/Multiplier Mode Counter Mode Tri-State / Mux Mode AT40K CARRY IN A ...

Page 9

RAM Dual-Ported RAM blocks are dispersed throughout the array as shown in Figure 7. A four-bit Input Data Bus connects to four horizontal local buses distributed over four sector rows (plane 1). A four-bit Output Data Bus ...

Page 10

Reading and writing the Dual-Port RAM are inde- pendent of each other. Reading the Dual-Port RAM is completely asynchronous. Latches are transparent; when Load is logic 1, data flows through; when Load is logic ...

Page 11

WE 2-to-4 Decoder Write Address Din(0) Din(1) Din(2) Din(3) Din Dout RAddr WAddr WE OE Din(4) Din(5) Din(6) Din(7) Din Dout RAddr WAddr WE OE Din Dout Din Dout WAddr RAddr RAddr WAddr Din Dout Din ...

Page 12

Clocking and Set/Reset Each of 8 dedicated Global Clock buses is connected to a dual-use Global Clock pad (GCK1 - GCK8). An internal sig- nal can be placed on a Global Clock bus by routing that sig- nal to a ...

Page 13

Figure 10. Clocking (for one column of cells) Express Bus (Plane 4; Half length at edge) "1" Global Clock Line (Buried) "1" Repeater "1" "1" AT40K } FCK (2 Per Edge Column of Cells) } GCK1 - GCK8 13 ...

Page 14

Figure 11. Set/Reset (for one column of cells) Repeater Express Bus (Plane 5; Half length at edge) Any User I/O can drive Global Set/Reset line AT40K 14 Each Cell has a programmable Set or Reset "1" Global Set/Reset line (Buried) ...

Page 15

Figure 12. West I/O (Mirrored for East I /O) PULL-DOWN PULL-DOWN "0 "1 "0 PULL- "1 PA (a) Primary "0 "1 "0 PULL- "1 PA (a) Secondary AT40K CEL CEL CEL CEL CEL 15 ...

Page 16

Figure 13. South I/O (Mirrored for North I/O) AT40K 16 CEL CEL DELA TRI- SCHMIT DRIV TTL/CMO VC PA (a) Primary CEL TRI- DRIV VC PA (a) Secondary CEL GN CEL DELA SCHMIT TTL/CMO GN ...

Page 17

Figure 14. North/West Corner, (similar for NE/SE/SW corners) VC DRIV TRI- PULL- PA PULL-DOWN TTL/CMO SCHMIT TRI- DELA "0 "1 "0 "1 AT40K PA GN TTL/CMO DRIV SCHMIT DELA CEL CEL CEL 17 ...

Page 18

Some of the bus resource on ATK40K is used as a dual- function resource. Table 1 shows which buses are used in a dual-function mode and which bus plane is used. The Table 1. Dual-Function Buses Function Type Cell Output ...

Page 19

Absolute Maximum Ratings - 5V Commercial/Industrial* Symbol Parameter V Supply Voltage CC ( Input Voltage Output Voltaage O T Storage Temperature STG T Junction Temperature J T Lead Temperature (Soldering, 10 sec.) L ESD Note: ...

Page 20

DC Characteristics - 5V Operation - Commercial/Industrial/Military Symbol Parameter V High-Level Input Voltage IH V Low-Level Input Voltage IL V High-Level Output Voltage OH V Low-Level Output Voltage OL I High-Level Input Current IH I Low-Level Input Current IL I ...

Page 21

AC Timing Characteristics - 5V Operation Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t Cell ...

Page 22

AC Timing Characteristics - 5V Operation Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Max delays are the average of t PDLH ...

Page 23

AC Timing Characteristics - 5V Operation Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Max delays are the average of t PDLH ...

Page 24

AC Timing Characteristics - 5V Operation Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Max delays are the average of t PDLH ...

Page 25

... ZAP ZAP AT40K05LV-4/3/2 AT40K10LV-4/3/2 AT40K20LV-4/3/2 AT40K40LV-4/3/2 Commercial ± 3.3V High (V ) 70% - 100% V IHC Low ( 30% V ILC AT40K Min Max -0.5 7.0 -0.5 7.0 -0.5 7.0 -65 C +150 C +150 C +250 C 2000 AT40K05LV-4/3/2 AT40K10LV-4/3/2 AT40K20LV-4/3/2 AT40K40LV-4/3/2 Industrial - ± 0.3V 3.3V 0.3V 70% - 100 30 Units ...

Page 26

DC Characteristics - 3.3V Operation - Commercial/Industrial Symbol Parameter V High-Level Input Voltage IH V Low-Level Input Voltage IL V High-Level Output Voltage OH V Low-Level Output Voltage OL I High-Level Input Current IH I Low-Level Input Current IL I ...

Page 27

AC Timing Characteristics - 3.3V Operation Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Max delays are the average of t PDLH ...

Page 28

AC Timing Characteristics - 3.3V Operation Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Max delays are the average of t PDLH ...

Page 29

AC Timing Characteristics - 3.3V Operation Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Max delays are the average of t PDLH ...

Page 30

... Read t (max) PXZ Notes: 1. CMOS buffer delays are measured from Buffer delay pad voltage of 1.5V with one output switching. 3. Parameter based on characterization and simulation; not tested in production. 4. Exact power calculation is available in Atmel FPGA Designer Software. AT40K 30 = 3.0V, temperature = 3.6V, temperature = Path ...

Page 31

Part/Package Availability AT40K05 PC 84 RQ100 VQ 100 TQ 144 PQ 160 PQ 208 PQ 240 PQ 304 BG 225 BG 352 BG 432 PG 475 USER I/O Counts - (Including Dual-Function Pins) AT40K05 100 VQ 100 ...

Page 32

AT40K05 AT40K10 AT40K20 AT40K40 128 I/O 192 I/O 256 I/O 384 I/O GND GND GND GND I/O1, I/O1, I/O1, I/O1, GCK1 GCK1 GCK1 GCK1 (A16) (A16) (A16) (A16) I/O2 I/O2 I/O2 I/O2 (A17) (A17) (A17) (A17) I/O3 I/O3 I/O3 I/O3 ...

Page 33

AT40K05 AT40K10 AT40K20 AT40K40 128 I/O 192 I/O 256 I/O 384 I/O I/O18 I/O22 I/O30 GND I/O31 I/O32 128 I/O 192 I/O 256 I/O 384 I/O I/O33 I/O34 I/O23 I/O35 I/O24 I/O36 GND GND VCC I/O37 I/O38 I/O25 I/O39 I/O26 ...

Page 34

AT40K05 AT40K10 AT40K20 AT40K40 128 I/O 192 I/O 256 I/O 384 I/O I/O63 I/O64 I/O65 I/O66 GND I/O31 I/O43 I/O67 I/O32 I/O44 I/O68 VCC VCC VCC 128 I/O 192 I/O 256 I/O 384 I/O I/O21 I/O33 I/O45 I/O69 I/O22 I/O34 ...

Page 35

AT40K05 AT40K10 AT40K20 AT40K40 128 I/O 192 I/O 256 I/O 384 I/O I/O32, I/O48, I/O64, I/O96, GCK2 GCK2 GCK2 GCK2 GND GND GND GND AT40K05 AT40K10 AT40K20 AT40K40 128 I/O 192 I/O ...

Page 36

AT40K05 AT40K10 AT40K20 AT40K40 128 I/O 192 I/O 256 I/O 384 I/O I/O41 I/O61 I/O81 I/O121 I/O42 I/O62 I/O82 I/O122 I/O43 I/O63 I/O83 I/O123 I/O44 I/O64 I/O84 I/O124 VCC VCC VCC I/O65 I/O85 I/O125 I/O66 I/O86 I/O126 GND I/O127 I/O128 ...

Page 37

AT40K05 AT40K10 AT40K20 AT40K40 128 I/O 192 I/O 256 I/O 384 I/O I/O104 I/O156 VCC GND GND I/O105 I/O157 I/O106 I/O158 I/O159 I/O160 I/O161 I/O162 GND I/O79 I/O107 I/O163 I/O80 I/O108 I/O164 VCC VCC VCC I/O53 I/O81 I/O109 I/O165 (D12) ...

Page 38

AT40K05 AT40K10 AT40K20 AT40K40 128 I/O 192 I/O 256 I/O 384 I/O I/O186 GND I/O187 I/O188 I/O61 I/O93 I/O125 I/O189 I/O62 I/O94 I/O126 I/O190 I/O63 I/O95 I/O127 I/O191 (D8) (D8) (D8) (D8) I/O64, I/O96, I/O128, I/O192 GCK4 GCK4 GCK4 ,GCK4 ...

Page 39

AT40K05 AT40K10 AT40K20 AT40K40 128 I/O 192 I/O 256 I/O 384 I/O I/O211 I/O212 I/O107 I/O141 I/O213 I/O108 I/O142 I/O214 I/O143 I/O215 I/O144 I/O216 GND GND GND GND I/O109 I/O145 I/O217 I/O110 I/O146 I/O218 I/O73, I/O111, I/O147, I/O219, FCK3 FCK3 ...

Page 40

AT40K05 AT40K10 AT40K20 AT40K40 128 I/O 192 I/O 256 I/O 384 I/O I/O244 I/O83 I/O123 I/O163 I/O245 I/O84 I/O124 I/O164 I/O246 GND I/O125 I/O165 I/O247 I/O126 I/O166 I/O248 I/O167 I/O249 I/O168 I/O250 I/O251 I/O252 VCC GND GND I/O169 I/O253 I/O170 ...

Page 41

AT40K05 AT40K10 AT40K20 AT40K40 128 I/O 192 I/O 256 I/O 384 I/O I/O90 I/O138 I/O184 I/O274 I/O275 I/O276 GND GND VCC VCC I/O91 I/O139 I/O185 I/O277 (D1) (D1) (D1) (D1) I/O92 I/O140 I/O186 I/O278 I/O279 I/O280 I/O281 I/O282 GND I/O187 ...

Page 42

AT40K05 AT40K10 AT40K20 AT40K40 128 I/O 192 I/O 256 I/O 384 I/O GND GND I/O151 I/O201 I/O301 I/O152 I/O202 I/O302 I/O103 I/O153 I/O203 I/O303 I/O104 I/O154 I/O204 I/O304 I/O305 I/O306 GND I/O307 I/O308 I/O155 I/O205 I/O309 I/O156 I/O206 I/O310 I/O207 ...

Page 43

AT40K05 AT40K10 AT40K20 AT40K40 128 I/O 192 I/O 256 I/O 384 I/O GND I/O331 I/O332 I/O333 I/O334 I/O111 I/O167 I/O223 I/O335 (A6) (A6) (A6) (A6) I/O112 I/O168 I/O224 I/O336 (A7) (A7) (A7) (A7) GND GND GND GND VCC VCC VCC ...

Page 44

AT40K05 AT40K10 AT40K20 AT40K40 128 I/O 192 I/O 256 I/O 384 I/O GND GND GND GND I/O241 I/O361 I/O242 I/O362 I/O181 I/O243 I/O363 I/O182 I/O244 I/O364 I/O365 I/O366 GND I/O367 I/O368 I/O121 I/O183 I/O245 I/O369 I/O122 I/O184 I/O246 I/O370 I/O123 ...

Page 45

Figure 15. AT40K20 Pad Ring GND I/O1,GCK1 (A16) I/O2 (A17) I/O3 I/O4 I/O5 (A18) I/O6 (A19) I/O7 I/O8 VCC GND I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 GND I/O17,FCK1 I/O18 I/O19 (A20) I/O20 (A21) VCC I/O21 I/O22 I/O23 I/O24 ...

Page 46

AT40K05 Ordering Information Usable Gates Speed Grade (ns) 5,000-10,000 2 5,000-10,000 2 Usable Gates Speed Grade (ns) 5,000-10,000 3 84J 84-lead, Plastic J-Leaded Chip Carrier (PLCC) 100Q 100-lead, Very Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (VQFP) 100RQ ...

Page 47

AT40K10 Ordering Information Usable Gates Speed Grade (ns) 10,000-20,000 2 10,000-20,000 2 Usable Gates Speed Grade (ns) 10,000-20,000 3 84J 84-lead, Plastic J-Leaded Chip Carrier (PLCC) 100Q 100-lead, Very Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (VQFP) 100RQ ...

Page 48

AT40K20 Ordering Information Usable Gates Speed Grade (ns) 20,000-30,000 2 20,000-30,000 2 Usable Gates Speed Grade (ns) 20,000-30,000 3 84J 84-lead, Plastic J-Leaded Chip Carrier (PLCC) 100Q 100-lead, Very Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (VQFP) 144Q ...

Page 49

... AT40K40-2CGC 432G AT40K40-2BQI 144Q AT40K40-2DQI 208Q AT40K40-2EQI 240Q AT40K40-2FQI 304Q AT40K40-2BGI 352G AT40K40-2CGI 432G Ordering Code Package AT40K40LV-3BQC 144Q AT40K40LV-3DQC 208Q AT40K40LV-3EQC 240Q AT40K40LV-3FQC 304Q AT40K40LV-3BGC 352G AT40K40LV-3CGC 432G Package Type AT40K Operation Range 5V Commercial ( Industrial (- Operation Range 3.3V Commercial ( ...

Page 50

Packaging Information 84J, 84-lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-018 AF 144Q, 144-lead, Plastic Gull Wing Quad Flat Package (TQFP) Dimensions in Millimeters and (Inches)* *Controlling dimension: millimeters AT40K 50 100Q, 100-lead, Plastic ...

Page 51

Packaging Information 208Q, 208-lead, Plastic Gull Wing Quad Flat Package (PQFP) Dimensions in (Millimeters) and Inches *Controlling dimension: millimeters 100RQ, 100-lead, Rectangular Plastic Gull Wing Quad Flat Pack (RQFP) Dimensions in Millimeters and (Inches)* 20.10 (0.791) 19.90 (0.783) PIN 1 ...

Page 52

Packaging Information 352B, 352-ball Ball Grid Array (BGA) Dimensions in (Millimeters) and Inches 1.38 (35.1 ) 1.37 (34.9) 1.38 (35.1) 1.37 (34.9) 0.062 (1.58) MAX (1.25 ...

Page 53

Thermal Coefficient Table Package Style Lead Count PQFP PQFP PQFP PQFP PQFP TQFP RQFP PLCC BGA BGA BGA Theta J-A 0 LFPM 144 33 160 30 208 32 240 27 304 19 100 47 100 225 26 ...

Page 54

... No licenses to patents or other intellectual prop- erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life suppor t devices or systems. ...

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