XC3030-100PC68C Xilinx Inc, XC3030-100PC68C Datasheet - Page 7

• Manufacturer Part Number: XC3030-100PC68C
• Description: IC LOGIC CL ARRAY 3000GAT 68PLCC
• Manufacturer: Xilinx Inc
• Series: XC3000r

Specifications of XC3030-100PC68C

• Number Of Labs/clbs: 100
• Total Ram Bits: 22176
• Number Of I /o: 58
• Number Of Gates: 2000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1012

IOB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads,
Propagation Delays (Input)
Set-up Time (Input)
Propagation Delays (Output)
Set-up and Hold Times (Output)
Clock
Global Reset Delays (based on XC3042)
Description
Pad to Direct In (I)
Pad to Registered In (Q) with latch transparent
Clock (IK) to Registered In (Q)
Pad to Clock (IK) set-up time
Clock (OK) to Pad
same
Output (O) to Pad
same
3-state to Pad begin hi-Z (fast)
same
3-state to Pad active and valid (fast)
same
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
Clock High time
Clock Low time
Max. flip-flop toggle rate
RESET Pad to Registered In (Q)
RESET Pad to output pad (fast)
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the
3. Input pad setup time and hold times are specified with respect to the internal clock (IK). To calculate system setup time,
see XAPP 024. Typical slew rate limited output rise/fall times are approximately four times longer.
internal pull-up resistor or alternatively configured as a driven output or driven from an external source.
subtract clock delay (clock pad to IK) from the specified input pad setup time value, but the subtracted value cannot be
less than zero (i.e., negative hold time). Negative hold time means that the delay in the input data is adequate for the
external system hold time to be zero, provided the input clock uses the Global signal distribution from pad to IK .
(fast)
(slew rate limited)
(fast)
(slew-rate limited)
(slew-rate limited)
(slew -rate limited)
(slew-rate limited)
2-159
Speed Grade
10
10
11
12
13
15
15
3
4
1
7
7
9
9
8
8
5
6
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
F
T
T
T
PID
PTG
IKRI
PICK
OKPO
OKPO
OPF
OPS
TSHZ
TSHZ
TSON
TSON
OOK
OKO
IOH
IOL
CLK
RRI
RPO
RPO
Min
20
10
70
0
5
5
-70
Max
5.5
21
13
33
29
28
14
34
25
35
53
6
9
8
Min Max
100
17
9
0
4
4
-100
17
10
27
23
25
12
29
24
33
45
4
4
6
8
Min Max
125
16
8
0
3
3
-125
16
24
20
24
11
27
23
29
42
3
3
9
5
7
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns