XC3042-100PC84C Xilinx Inc, XC3042-100PC84C Datasheet

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XC3042-100PC84C

Manufacturer Part Number
XC3042-100PC84C
Description
IC LOGIC CL ARRAY 4200GAT 84PLCC
Manufacturer
Xilinx Inc
Series
XC3000r
Datasheet

Specifications of XC3042-100PC84C

Number Of Labs/clbs
144
Total Ram Bits
30784
Number Of I /o
74
Number Of Gates
3000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
84-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Logic Elements/cells
-
Other names
122-1020

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Features
Industry-leading FPGA family with five device types
– Logic densities from 1,000 to 6,000 gates
– Up to 144 user-definable I/Os
Guaranteed 70- to 125-MHz toggle rates, 9 to 5.5 ns
logic delays
Advanced CMOS static memory technology
– Low quiescent and active power consumption
XC3000-specific features
– Ultra-low current option in Power-Down mode
– 4-mA output sink and source current
– Broad range of package options includes plastic and
– 100% bitstream compatible with the XC3100 family
– Commercial, industrial, military, “high rel”, and MIL-
– Easy migration to XC3300 series of HardWire mask-
Device
XC3020
XC3030
XC3042
XC3064
XC3090
ceramic quad flat packs, plastic leaded chip carriers
and pin grid arrays
STD-883 Class B grade devices
programmed devices for high-volume production
CLBs
100
144
224
320
64
All new designs should use XC3000A.
Information on XC3000 is presented here
as a reference for existing designs.
XC3000 bitstreams are upward compatible
to XC3000A without modification.
IMPORTANT NOTICE
10 x 10
12 x 12
16 x 14
16 x 20
8 x 8
Array
User I/Os
Max
120
144
64
80
96
2-153
XC3000
Logic Cell Array Family
Product Specification
Description
XC3000 is the original family of devices in the XC3000
class of Field Programmable Gate Array (FPGA) architec-
tures. The XC3000 family has a proven track record in
addressing a wide range of design applications, including
general logic replacement and sub-systems integration.
For a thorough description of the XC3000 architecture see
the preceding pages of this data book.
The XC3000 Family covers a range of nominal device
densities from 2,000 to 9,000 gates, practically achievable
densities from 1,000 to 6,000 gates. Device speeds,
described in terms of maximum guaranteed toggle fre-
quencies, range from 70 to 125 MHz. The performance of
a completed design depends upon placement and routing
implementation, so, like with any gate array, the final
verification of device utilization and performance can only
be known after the design has been placed and routed.
Flip-Flops
256
360
480
688
928
Horizontal
Longlines
16
20
24
32
40
Configuration
Data Bits
14,779
22,176
30,784
46,064
64,160

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XC3042-100PC84C Summary of contents

Page 1

... Commercial, industrial, military, “high rel”, and MIL- STD-883 Class B grade devices – Easy migration to XC3300 series of HardWire mask- programmed devices for high-volume production Device CLBs XC3020 64 XC3030 100 XC3042 144 XC3064 224 XC3090 320 IMPORTANT NOTICE XC3000 Logic Cell Array Family Product Specification ...

Page 2

XC3000 Logic Cell Array Family Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. Absolute Maximum Ratings Symbol ...

Page 3

... CC(MAX) MAX 2 CCPD = 0 V (sample tested) IN tested and guaranteed 3 can be ordered with a CCPD CC XC3020 SPC0107 CCPD XC3030 SPC0107 CCPD XC3042 SPC0107 CCPD XC3064 SPC0107 CCPD XC3090 SPC0107 CCPD 2-155 Min Max 3.86 Commercial 0.40 3.76 ) Industrial 0.40 2.30 XC3020 50 XC3030 ...

Page 4

... T to L.L. active and valid with single pull-up resistor T to L.L. active and valid with pair of pull-up resistors T to L.L. High with single pull-up resistor T to L.L. High with pair of pull-up resistors BIDI Bidirectional buffer delay * Timing is based on the XC3042, for other devices see XACT timing calculator ILO ICK ...

Page 5

... RD width delay from rd to outputs Global Reset (RESET Pad)* RESET width (Low) delay from RESET pad to outputs *Timing is based on the XC3042, for other devices see XACT timing calculator. Note: The CLB output delay (T the Data In hold time requirement (T Speed Grade Symbol ...

Page 6

XC3000 Logic Cell Array Family IOB Switching Characteristic Guidelines I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output (Registered) I/O Pad TS I/O Pad Output 3- ...

Page 7

... Clock Clock High time Clock Low time Max. flip-flop toggle rate Global Reset Delays (based on XC3042) RESET Pad to Registered In (Q) RESET Pad to output pad (fast) (slew-rate limited) Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads, see XAPP 024 ...

Page 8

... CODE -50 - XC3020 -100 -125 C C -50 - XC3030 -100 -125 -50 - XC3042 -100 C I -125 C -50 - XC3064 -100 C I -125 C -50 - XC3090 -100 C I -125 Commercial = 0 to +70 C Parentheses indicate future product plans XC3030-70PC44C Package Type 84 100 TOP- PLAST. PLAST. BRAZED PLAST. CERAM. PLAST. ...

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