IC LOGIC CL ARRAY 3000GAT 84PLCC

XC3030A-7PC84C

Manufacturer Part NumberXC3030A-7PC84C
DescriptionIC LOGIC CL ARRAY 3000GAT 84PLCC
ManufacturerXilinx Inc
SeriesXC3000A/L
XC3030A-7PC84C datasheet
 

Specifications of XC3030A-7PC84C

Number Of Labs/clbs100Total Ram Bits22176
Number Of I /o74Number Of Gates2000
Voltage - Supply4.75 V ~ 5.25 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case84-LCC (J-Lead)
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantNumber Of Logic Elements/cells-
Other names122-1018  
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Product Obsolete or Under Obsolescence
R
November 9, 1998 (Version 3.1)
Features
• Complete line of four related Field Programmable Gate
Array product families
- XC3000A, XC3000L, XC3100A, XC3100L
• Ideal for a wide range of custom VLSI design tasks
- Replaces TTL, MSI, and other PLD logic
- Integrates complete sub-systems into a single
package
- Avoids the NRE, time delay, and risk of conventional
masked gate arrays
• High-performance CMOS static memory technology
- Guaranteed toggle rates of 70 to 370 MHz, logic
delays from 7 to 1.5 ns
- System clock speeds over 85 MHz
- Low quiescent and active power consumption
• Flexible FPGA architecture
- Compatible arrays ranging from 1,000 to 7,500 gate
complexity
- Extensive register, combinatorial, and I/O
capabilities
- High fan-out signal distribution, low-skew clock nets
- Internal 3-state bus capabilities
- TTL or CMOS input thresholds
- On-chip crystal oscillator amplifier
• Unlimited reprogrammability
- Easy design iteration
- In-system logic changes
• Extensive packaging options
- Over 20 different packages
- Plastic and ceramic surface-mount and pin-grid-
array packages
- Thin and Very Thin Quad Flat Pack (TQFP and
VQFP) options
• Ready for volume production
- Standard, off-the-shelf product availability
- 100% factory pre-tested devices
- Excellent reliability record
Max Logic
Device
Gates
XC3020A, 3020L, 3120A
1,500
XC3030A, 3030L, 3130A
2,000
XC3042A, 3042L, 3142A, 3142L
3,000
XC3064A, 3064L, 3164A
4,500
XC3090A, 3090L, 3190A, 3190L
6,000
XC3195A
7,500
November 9, 1998 (Version 3.1)
0
XC3000 Series
Field Programmable Gate Arrays
(XC3000A/L, XC3100A/L)
Product Description
0
7*
• Complete Development System
- Schematic capture, automatic place and route
- Logic and timing simulation
- Interactive design editor for design optimization
- Timing calculator
- Interfaces to popular design environments like
Viewlogic, Cadence, Mentor Graphics, and others
Additional XC3100A Features
• Ultra-high-speed FPGA family with six members
- 50-85 MHz system clock rates
- 190 to 370 MHz guaranteed flip-flop toggle rates
- 1.55 to 4.1 ns logic delays
• High-end additional family member in the 22 X 22 CLB
array-size XC3195A device
• 8 mA output sink current and 8 mA source current
• Maximum power-down and quiescent current is 5 mA
• 100% architecture and pin-out compatible with other
XC3000 families
• Software and bitstream compatible with the XC3000,
XC3000A, and XC3000L families
XC3100A combines the features of the XC3000A and
XC3100 families:
• Additional interconnect resources for TBUFs and CE
inputs
• Error checking of the configuration bitstream
• Soft startup holds all outputs slew-rate limited during
initial power-up
• More advanced CMOS process
Low-Voltage Versions Available
• Low-voltage devices function at 3.0 - 3.6 V
• XC3000L - Low-voltage versions of XC3000A devices
• XC3100L - Low-voltage versions of XC3100A devices
Typical Gate
User I/Os
CLBs
Array
Range
Max
1,000 - 1,500
64
8 x 8
64
1,500 - 2,000
100
10 x 10
80
2,000 - 3,000
144
12 x 12
96
3,500 - 4,500
224
16 x 14
120
5,000 - 6,000
320
16 x 20
144
6,500 - 7,500
484
22 x 22
176
Horizontal
Configuration
Flip-Flops
Longlines
Data Bits
256
16
14,779
360
20
22,176
480
24
30,784
688
32
46,064
928
40
64,160
1,320
44
94,984
7-3
7

XC3030A-7PC84C Summary of contents

  • Page 1

    ... Ready for volume production - Standard, off-the-shelf product availability - 100% factory pre-tested devices - Excellent reliability record Max Logic Device Gates XC3020A, 3020L, 3120A 1,500 XC3030A, 3030L, 3130A 2,000 XC3042A, 3042L, 3142A, 3142L 3,000 XC3064A, 3064L, 3164A 4,500 XC3090A, 3090L, 3190A, 3190L 6,000 XC3195A 7,500 November 9, 1998 (Version 3 ...

  • Page 2

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays Introduction XC3000-Series Field Programmable Gate Arrays (FPGAs) provide a group of high-performance, high-density, digital integrated circuits. Their regular, extendable, flexible, user-programmable array architecture is composed of a configuration program ...

  • Page 3

    Product Obsolete or Under Obsolescence R Improvements in the XC3000A and XC3000L Families The XC3000A and XC3000L families offer the following enhancements over the popular XC3000 family: The XC3000A and XC3000L families have additional inter- connect resources to drive the ...

  • Page 4

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays Detailed Functional Description The perimeter of configurable Input/Output Blocks (IOBs) provides a programmable interface between the internal logic array and the device package pins. The array of Con- figurable ...

  • Page 5

    Product Obsolete or Under Obsolescence R Read or Write Data Figure 3: Static Configuration Memory Cell loaded with one bit of configuration program and con- trols one program selection in the Field Programmable Gate Array. The memory cell ...

  • Page 6

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays The input-buffer portion of each IOB provides threshold detection to translate external signals applied to the pack- age pin to internal logic levels. The global input-buffer threshold of the ...

  • Page 7

    Product Obsolete or Under Obsolescence R Configurable Logic Block The array of CLBs provides the functional elements from which the user’s logic is constructed. The logic blocks are arranged in a matrix within the perimeter of IOBs. For example, the ...

  • Page 8

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays Flexible routing allows use of common or individual CLB clocking. The combinatorial-logic portion of the CLB uses look-up table to implement Boolean functions. Variables selected ...

  • Page 9

    Product Obsolete or Under Obsolescence R Count Enable Parallel Enable Clock Dual Function of 4 Variables D0 D1 Function of 5 Variables D2 Function of 6 Variables Figure 7: Counter. The modulo-8 binary counter with parallel enable and clock enable ...

  • Page 10

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays Figure 9: Design Editor Locations of interconnect access, CLB control inputs, logic inputs and outputs. The dot pattern represents the available programmable interconnection points (PIPs). Some of the interconnect ...

  • Page 11

    Product Obsolete or Under Obsolescence R Figure 10: FPGA General-Purpose Interconnect. Composed of a grid of metal segments that may be inter- connected through switch matrices to form networks for CLB and IOB inputs and outputs. Figure 11: Switch Matrix ...

  • Page 12

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays Global Buffer Direct Input * Unbonded IOBs (6 Places) Figure 13: XC3020A Die-Edge IOBs. The XC3020A die-edge IOBs are provided with direct access to adjacent CLBs. 7-14 Global Buffer ...

  • Page 13

    Product Obsolete or Under Obsolescence R Longlines The Longlines bypass the switch matrices and are intended primarily for signals that must travel a long distance, or must have minimum skew among multiple destinations. Longlines, shown in Figure 14, run vertically ...

  • Page 14

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays Figure 15: Programmable Interconnection of Longlines. This is provided at the edges of the routing area. Three-state buffers allow the use of horizontal Longlines to form on-chip wired AND ...

  • Page 15

    Product Obsolete or Under Obsolescence R A buffer in the upper left corner of the FPGA chip drives a global net which is available to all K inputs of logic blocks. Using the global buffer for a clock signal provides ...

  • Page 16

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays Crystal Oscillator Figure 18 also shows the location of an internal high speed inverting amplifier that may be used to implement an on-chip crystal oscillator associated with ...

  • Page 17

    ... Program Mode Low on DONE/PROGRAM and RESET Clear Is ~ 200 Cycles for the XC3020A—130 to 400 s ~ 250 Cycles for the XC3030A—165 to 500 s ~ 290 Cycles for the XC3042A—195 to 580 s ~ 330 Cycles for the XC3064A—220 to 660 s ~ 375 Cycles for the XC3090A—250 to 750 s shows the state sequences ...

  • Page 18

    ... Program Length —Dummy Bits (4 Bits Minimum) For XC3120 197 Configuration Data Frames (Each Frame Consists of: A Start Bit (0) A 71-Bit Data Field Three Stop Bits Postamble Code (4 Bits Minimum) XC3042A XC3030A XC3042L XC3030L XC3142A XC3130A XC3142L 1,500 to 2,000 2,000 to 3,000 64 100 ...

  • Page 19

    Product Obsolete or Under Obsolescence R a synchronous start-up sequence and become operational. See Figure 22. Two CCLK cycles after the completion of loading configuration data, the user I/O pins are enabled as configured. As selected, the internal user-logic RESET ...

  • Page 20

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays be used to drive the remaining unused routing, as that might affect timing of user nets. Tie can be omitted for quick breadboard iterations where a few additional milliamps ...

  • Page 21

    Product Obsolete or Under Obsolescence R Special Configuration Functions The configuration data includes control over several spe- cial functions in addition to the normal user logic functions and interconnect. • Input thresholds • Readback disable • DONE pull-up resistor • ...

  • Page 22

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays RESET Timing As with DONE timing, the timing of the release of the inter- nal reset can be controlled to occur either a CCLK cycle before, or after, the ...

  • Page 23

    Product Obsolete or Under Obsolescence R Configuration Timing This section describes the configuration modes in detail. Master Serial Mode In Master Serial mode, the CCLK output of the lead FPGA drives a Xilinx Serial PROM that feeds the DIN input. ...

  • Page 24

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays CCLK (Output DSCK Serial Data In n Serial DOUT n – 3 (Output) Description Data In setup CCLK Data In hold Notes power-up, V must ...

  • Page 25

    Product Obsolete or Under Obsolescence R Master Parallel Mode In Master Parallel mode, the lead FPGA directly addresses an industry-standard byte-wide EPROM and accepts eight data bits right before incrementing (or decrementing) the address outputs. The eight data bits are ...

  • Page 26

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays A0-A15 (output) D0-D7 RCLK (output) CCLK (output) DOUT (output) Description To address valid To data setup RCLK To data hold RCLK High RCLK Low Notes power-up, V ...

  • Page 27

    Product Obsolete or Under Obsolescence R Peripheral Mode Peripheral mode uses the trailing edge of the logic AND condition of the CS0, CS1, CS2, and WS inputs to accept byte-wide data from a microprocessor bus. In the lead FPGA, this ...

  • Page 28

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays WRITE TO FPGA WS, CS0, CS1 CS2 T CA D0-D7 CCLK 4 RDY/BUSY DOUT Description Effective Write time required (Assertion of CS0, CS1, CS2, WS) DIN Setup time required ...

  • Page 29

    Product Obsolete or Under Obsolescence R Slave Serial Mode In Slave Serial mode, an external signal drives the CCLK input(s) of the FPGA(s). The serial configuration bitstream must be available at the DIN input of the lead FPGA a short ...

  • Page 30

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays DIN Bit DCC CCLK DOUT (Output) Description To DOUT DIN setup CCLK DIN hold High time Low time (Note 1) Frequency Notes: 1. The max limit ...

  • Page 31

    Product Obsolete or Under Obsolescence R Program Readback Switching Characteristics DONE/PROG (OUTPUT) RTRIG (M0) 4 CCLK( CCRD HI-Z M1 Input/ RDATA Output Description RTRIG RTRIG High RTRIG setup RDATA delay CCLK High time Low time Notes: 1. During ...

  • Page 32

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays General XC3000 Series Switching Characteristics RESET M0/M1/ DONE/PROG INIT User State (Output) PWRDWN V (Valid) CC Description M0, M1, M2 setup time required RESET ...

  • Page 33

    Product Obsolete or Under Obsolescence R Device Performance The XC3000 families of FPGAs can achieve very high per- formance. This is the result of • A sub-micron manufacturing process, developed and continuously being enhanced for the production of state-of-the-art CMOS ...

  • Page 34

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays 1.00 0.80 0.60 0.40 0.20 – 55 – 40 – 20 Figure 32: Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations 300 250 200 150 ...

  • Page 35

    Product Obsolete or Under Obsolescence R Dynamic Power Consumption One CLB driving three local interconnects One global clock buffer and clock line One device output with load Power Consumption The Field Programmable Gate Array exhibits the low ...

  • Page 36

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays Pin Descriptions Permanently Dedicated Pins V CC Two to eight (depending on package type) connections to the positive V supply voltage. All must be connected. GND Two to eight ...

  • Page 37

    Product Obsolete or Under Obsolescence R AND of several slave mode devices, a hold-off signal for a master mode device. After configuration this pin becomes a user-programmable I/O pin. BCLKIN This is a direct CMOS level input to the alternate ...

  • Page 38

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays Pin Functions During Configuration Configuration Mode <M2:M1:M0> SLAVE MASTER- MASTER- SERIAL SERIAL PERIPH HIGH <1:1:1> <0:0:0> <1:0:1> <1:1:0> POWR POWER POWER POWER DWN DWN DWN DWN (I) (I) (I) ...

  • Page 39

    Product Obsolete or Under Obsolescence R XC3000A Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. ...

  • Page 40

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3000A Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage ...

  • Page 41

    Product Obsolete or Under Obsolescence R XC3000A CLB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they ...

  • Page 42

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3000A CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) CLB Input (A,B,C,D,E) CLB Clock CLB Input (Direct In) CLB Input (Enable Clock) CLB Output (Flip-Flop) CLB Input ...

  • Page 43

    Product Obsolete or Under Obsolescence R XC3000A IOB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they ...

  • Page 44

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3000A IOB Switching Characteristics Guidelines (continued) I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output ...

  • Page 45

    Product Obsolete or Under Obsolescence R XC3000L Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. ...

  • Page 46

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3000L Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage ...

  • Page 47

    Product Obsolete or Under Obsolescence R XC3000L CLB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they ...

  • Page 48

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3000L CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) CLB Input (A,B,C,D,E) CLB Clock CLB Input (Direct In) CLB Input (Enable Clock) CLB Output (Flip-Flop) CLB Input ...

  • Page 49

    Product Obsolete or Under Obsolescence R XC3000L IOB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they ...

  • Page 50

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3000L IOB Switching Characteristics Guidelines (continued) I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output ...

  • Page 51

    Product Obsolete or Under Obsolescence R XC3100A Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. ...

  • Page 52

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3100A Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage ...

  • Page 53

    Product Obsolete or Under Obsolescence R XC3100A CLB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they ...

  • Page 54

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3100A CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) CLB Input (A,B,C,D,E) CLB Clock CLB Input (Direct In) CLB Input (Enable Clock) CLB Output (Flip-Flop) CLB Input ...

  • Page 55

    Product Obsolete or Under Obsolescence R XC3100A IOB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they ...

  • Page 56

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3100A IOB Switching Characteristics Guidelines (continued) I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output ...

  • Page 57

    Product Obsolete or Under Obsolescence R XC3100L Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. ...

  • Page 58

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3100L Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage ...

  • Page 59

    Product Obsolete or Under Obsolescence R XC3100L CLB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they ...

  • Page 60

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3100L CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) CLB Input (A,B,C,D,E) CLB Clock CLB Input (Direct In) CLB Input (Enable Clock) CLB Output (Flip-Flop) CLB Input ...

  • Page 61

    Product Obsolete or Under Obsolescence R XC3100L IOB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they ...

  • Page 62

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3100L IOB Switching Characteristics Guidelines (continued) I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output ...

  • Page 63

    ... M1-RDATA 17 M0-RTRIG 18 M2-I/O 19 HDC-I/O 20 LDC-I/O 21 I/O 22 INIT-I/O Peripheral mode and Master Parallel mode are not supported in the PC44 package November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays Pin No. XC3030A 23 GND 24 I/O 25 I/O 26 XTL2(IN)-I/O 27 RESET 28 DONE-PGM 29 I/O 30 XTL1(OUT)-BCLK-I/O ...

  • Page 64

    ... A10-I/O 16 A9-I/O 17 PWRDN 18 TCLKIN-I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 VCC 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 M1-RDATA 32 M0-RTRIG 7-66 Pin No. XC3030A 33 M2-I/O 34 HDC-I/O 35 I/O 36 LDC-I/O 37 I/O 38 I/O 39 I/O 40 INIT-I/O 41 GND 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 XTAL2(IN)-I/O 48 RESET 49 DONE-PG 50 D7-I/O 51 XTAL1(OUT)-BCLKIN-I/O ...

  • Page 65

    ... This table describes the pinouts of three different chips in three different packages. The pin-description column lists 84 of the 118 pads on the XC3042A (and 84 of the 98 pads on the XC3030A) that are connected to the 84 package pins. Ten pads, indicated by an asterisk, do not exist on the XC3020A, which has 74 pads; therefore the corresponding pins on the 84-pin packages have no connections to an XC3020A. Six pads on the XC3020A and 16 pads on the XC3030A, indicated by a dash (— ...

  • Page 66

    ... Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited the PC84 package, XC3064A, XC3090A and XC3195A have additional VCC and GND pins and thus a different pin definition than XC3020A/XC3030A/XC3042A. 7-68 PLCC Pin Number ...

  • Page 67

    ... XC3042A that are connected to the 100 package pins. Two pads, indicated by double asterisks, do not exist on the XC3030A, which has 98 pads; therefore the corresponding pins have no connections. Twenty-six pads, indicated by single or double asterisks, do not exist on the XC3020A, which has 74 pads; therefore, the corresponding pins have no connections ...

  • Page 68

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3000 Series 132-Pin Ceramic and Plastic PGA Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts PGA PGA Pin XC3042A Pin Number XC3064A Number C4 GND B13 A1 ...

  • Page 69

    Product Obsolete or Under Obsolescence R XC3000 Series 144-Pin Plastic TQFP Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts XC3042A Pin XC3064A Number XC3090A 1 PWRDN 2 I/O-TCLKIN 3 I/O* 4 I/O 5 I/O 6 I/O* 7 I/O ...

  • Page 70

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3000 Series 160-Pin PQFP Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts PQFP Pin XC3064A, XC3090A, PQFP Pin Number XC3195A Number 1 I/ I/O* 42 ...

  • Page 71

    Product Obsolete or Under Obsolescence R XC3000 Series 175-Pin Ceramic and Plastic PGA Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts PGA Pin PGA Pin XC3090A, XC3195A Number Number B2 PWRDN D13 D4 TCLKIN-I/O B14 B3 I/O C14 ...

  • Page 72

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3000 Series 176-Pin TQFP Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts Pin Pin XC3090A Number Number 1 PWRDWN 45 2 TCLKIN-I I ...

  • Page 73

    Product Obsolete or Under Obsolescence R XC3000 Series 208-Pin PQFP Pinouts XC3000A, and XC3000L families have identical pinouts Pin Number XC3090A Pin Number 1 – GND 54 3 PWRDWN 55 4 TCLKIN-I I I/O ...

  • Page 74

    Product Obsolete or Under Obsolescence XC3000 Series Field Programmable Gate Arrays XC3195A PQ208 Pinouts Pin Description PQ208 Pin Description A9-I/O 206 A10-I/O 205 I/O 204 I/O 203 I/O 202 I/O 201 RDY/BUSY-RCLK-I/O A8-I/O 200 A11-I/O 199 I/O 198 I/O 197 ...

  • Page 75

    ... Product Obsolete or Under Obsolescence R Product Availability Pins Plast. Plast. Plast. Type PLCC VQFP PLCC Code PC44 VQ64 PC68 -7 CI XC3020A - XC3030A - XC3042A -6 -7 XC3064A -6 -7 XC3090A -6 XC3020L -8 XC3030L -8 CI XC3042L -8 XC3064L -8 XC3090L - XC3120A - - XC3130A - - XC3142A - XC3164A - XC3190A - XC3195A ...

  • Page 76

    ... I = Industrial -40 to +100 C J Number of Package Pins 100 132 110 70 70 XC3030A-3 PC44C Temperature Range Number of Pins Package Type Revision 144 160 175 176 208 Plast. Plast. Plast. Cer. Plast. Plast. TQFP PQFP PGA PGA TQFP PQFP PP175 PG175 TQ176 PQ208 ...