XC3030A-7PC84C Xilinx Inc, XC3030A-7PC84C Datasheet - Page 17

• Manufacturer Part Number: XC3030A-7PC84C
• Description: IC LOGIC CL ARRAY 3000GAT 84PLCC
• Manufacturer: Xilinx Inc
• Series: XC3000A/Lr

Specifications of XC3030A-7PC84C

• Number Of Labs/clbs: 100
• Total Ram Bits: 22176
• Number Of I /o: 74
• Number Of Gates: 2000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1018

Configuration
Initialization Phase
An internal power-on-reset circuit is triggered when power
is applied. When V
of the FPGA device begin to operate (nominally 2.5 to 3 V),
the programmable I/O output buffers are 3-stated and a
high-impedance pull-up resistor is provided for the user
I/O pins. A time-out delay is initiated to allow the power
supply voltage to stabilize. During this time the power-down
mode is inhibited. The Initialization state time-out (about 11
to 33 ms) is determined by a 14-bit counter driven by a
self-generated internal timer. This nominal 1-MHz timer is
subject to variations with process, temperature and power
supply. As shown in
choices are available as determined by the input levels of
three mode pins; M0, M1 and M2.
Table 1: Configuration Mode Choices
November 9, 1998 (Version 3.1)
Figure 20: A State Diagram of the Configuration Process for Power-up and Reprogram.
M0 M1 M2 CCLK
0
0
0
0
1
1
1
1
Power-On Delay is
0
0
1
1
0
0
1
1
2
2
14
16
Configuration
Initialization
Time Delay
Power-On
Memory
Cycles for Non-Master Mode—11 to 33 ms
Cycles for Master Mode—43 to 130 ms
0 output
1 output
0 —
1 output
0 —
1 output
0 —
1 input
Clear
INIT Output = Low
R
All User I/O Pins 3-Stated with High Impedance Pull-Up, HDC=High, LDC=Low
CC
Master
Master
reserved
Master
reserved
Peripheral Byte Wide
reserved
Slave
reaches the voltage at which portions
Mode
Product Obsolete or Under Obsolescence
Table
RESET
Active
1, five configuration mode
Bit Serial
Byte Wide Addr. = 0000 up
—
Byte Wide Addr. = FFFF down
—
—
Bit Serial
No
Active RESET
Data
Mode Pins
Low on DONE/PROGRAM and RESET
Test
XC3000 Series Field Programmable Gate Arrays
Program Mode
Configuration
tialization and Clear states are complete. The FPGA tests
for the absence of an external active Low RESET before it
makes a final sample of the mode lines and enters the Con-
figuration state. An external wired-AND of one or more INIT
pins can be used to control configuration by the assertion of
the active-Low RESET of a master mode device or to sig-
nal a processor that the FPGAs are not yet initialized.
If a configuration has begun, a re-assertion of RESET for a
minimum of three internal timer cycles will be recognized
and the FPGA will initiate an abort, returning to the Clear
state to clear the partially loaded configuration memory
words. The FPGA will then resample RESET and the mode
lines before re-entering the Configuration state.
During configuration, the XC3000A, XC3000L, XC3100A,
and XC3100L devices check the bit-stream format for stop
bits in the appropriate positions. Any error terminates the
configuration and pulls INIT Low.
In Master configuration modes, the device becomes the
source of the Configuration Clock (CCLK). The beginning
of configuration of devices using Peripheral or Slave
modes must be delayed long enough for their initialization
to be completed. An FPGA with mode lines selecting a
Master configuration mode extends its initialization state
using four times the delay (43 to 130 ms) to assure that all
daisy-chained slave devices, which it may be driving, will
be ready even if the master is very fast, and the slave(s)
very slow.
of Initialization, the device enters the Clear state where it
clears the configuration memory. The active Low,
open-drain initialization signal INIT indicates when the Ini-
Figure 20
Clear Is
~ 200 Cycles for the XC3020A—130 to 400 s
~ 250 Cycles for the XC3030A—165 to 500 s
~ 290 Cycles for the XC3042A—195 to 580 s
~ 330 Cycles for the XC3064A—220 to 660 s
~ 375 Cycles for the XC3090A—250 to 750 s
Start-Up
shows the state sequences. At the end
PWRDWN
Inactive
No HDC, LDC
Power Down
Operational
or Pull-Up
Mode
Active RESET
PWRDWN
Operates on
User Logic
Active
X3399
7-19
7