IC LOGIC CL ARRAY 3000GAT 84PLCC

XC3030A-7PC84C

Manufacturer Part NumberXC3030A-7PC84C
DescriptionIC LOGIC CL ARRAY 3000GAT 84PLCC
ManufacturerXilinx Inc
SeriesXC3000A/L
XC3030A-7PC84C datasheet
 


Specifications of XC3030A-7PC84C

Number Of Labs/clbs100Total Ram Bits22176
Number Of I /o74Number Of Gates2000
Voltage - Supply4.75 V ~ 5.25 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case84-LCC (J-Lead)
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantNumber Of Logic Elements/cells-
Other names122-1018  
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Page 23/76

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Product Obsolete or Under Obsolescence
R
Configuration Timing
This section describes the configuration modes in detail.
Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA
drives a Xilinx Serial PROM that feeds the DIN input. Each
rising edge of the CCLK output increments the Serial
PROM internal address counter. This puts the next data bit
on the SPROM data output, connected to the DIN pin. The
lead FPGA accepts this data on the subsequent rising
CCLK edge.
The lead FPGA then presents the preamble data (and all
data that overflows the lead device) on its DOUT pin. There
is an internal delay of 1.5 CCLK periods, which means that
*
IF READBACK IS
ACTIVATED, A
5-k RESISTOR IS
REQUIRED IN
SERIES WITH M1
DURING CONFIGURATION
THE 5 k M2 PULL-DOWN
RESISTOR OVERCOMES THE
INTERNAL PULL-UP,
BUT IT ALLOWS M2 TO
+5V
BE USER I/O.
GENERAL-
PURPOSE
USER I/O
PINS
RESET
Figure 23: Master Serial Mode Circuit Diagram
November 9, 1998 (Version 3.1)
XC3000 Series Field Programmable Gate Arrays
DOUT changes on the falling CCLK edge, and the next
device in the daisy-chain accepts data on the subsequent
rising CCLK edge.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a permanently High user output. Using
DONE also avoids contention on DIN, provided the early
DONE option is invoked.
+5 V
*
M0
M1
PWRDWN
TO DIN OF OPTIONAL
DAISY-CHAINED LCAs WITH
DOUT
DIFFERENT CONFIGURATIONS
M2
TO CCLK OF OPTIONAL
DAISY-CHAINED LCAs WITH
HDC
DIFFERENT CONFIGURATIONS
LDC
INIT
OTHER
I/O PINS
TO CCLK OF OPTIONAL
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
XC3000
TO DIN OF OPTIONAL
FPGA
SLAVE LCAs WITH IDENTICAL
DEVICE
CONFIGURATIONS
+5 V
RESET
V CC
DIN
DATA
CCLK
CLK
SCP
D/P
CE
INIT
OE/RESET
XC17xx
(LOW RESETS THE XC17xx ADDRESS POINTER)
V PP
DATA
CLK
CASCADED
SERIAL
CE
CEO
MEMORY
OE/RESET
X5989_01
7-25
7