IC LOGIC CL ARRAY 3000GAT 84PLCC

XC3030A-7PC84C

Manufacturer Part NumberXC3030A-7PC84C
DescriptionIC LOGIC CL ARRAY 3000GAT 84PLCC
ManufacturerXilinx Inc
SeriesXC3000A/L
XC3030A-7PC84C datasheet
 


Specifications of XC3030A-7PC84C

Number Of Labs/clbs100Total Ram Bits22176
Number Of I /o74Number Of Gates2000
Voltage - Supply4.75 V ~ 5.25 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case84-LCC (J-Lead)
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantNumber Of Logic Elements/cells-
Other names122-1018  
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Product Obsolete or Under Obsolescence
R
Master Parallel Mode
In Master Parallel mode, the lead FPGA directly addresses
an industry-standard byte-wide EPROM and accepts eight
data bits right before incrementing (or decrementing) the
address outputs.
The eight data bits are serialized in the lead FPGA, which
then presents the preamble data (and all data that over-
flows the lead device) on the DOUT pin. There is an inter-
*
+5 V
+5 V
*
If Readback is
Activated, a
5-k Resistor is
M0 M1PWRDWN
Required in
Series With M1
5 k
CCLK
DOUT
M2
HDC
RCLK
A15
General-
A14
Purpose
User I/O
A13
Pins
A12
Other
A11
I/O Pins
A10
FPGA
Master
A9
D7
A8
D6
A7
D5
A6
D4
A5
D3
A4
D2
A3
D1
A2
D0
A1
A0
D/P
RESET
INIT
N.C.
Reprogram
System Reset
Figure 25: Master Parallel Mode Circuit Diagram
November 9, 1998 (Version 3.1)
XC3000 Series Field Programmable Gate Arrays
nal delay of 1.5 CCLK periods, after the rising CCLK edge
that accepts a byte of data, and also changes the EPROM
address, until the falling CCLK edge that makes the LSB
(D0) of this byte appear at DOUT. This means that DOUT
changes on the falling CCLK edge, and the next device in
the daisy chain accepts data on the subsequent rising
CCLK edge.
*
+5 V
M0 M1PWRDWN
CCLK
DOUT
DIN
FPGA
Slave #1
M2
A15
HDC
A14
LDC
A13
EPROM
Other
A12
I/O Pins
A11
A10
INIT
A9
D/P
A8
RESET
A7
D7
A6
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0
D0
OE
CE
8
Open
Collector
*
+5 V
M0 M1PWRDWN
5 k
5 k
CCLK
DOUT
DIN
...
FPGA
Slave #n
M2
HDC
General-
General-
LDC
Purpose
Purpose
User I/O
User I/O
Pins
Pins
Other
I/O Pins
INIT
D/P
Reset
Note: XC2000 Devices Do Not
Have INIT to Hold Off a Master
Device. Reset of a Master Device
Should be Asserted by an External
Timing Circuit to Allow for LCA CCLK
Variations in Clear State Time.
+5 V
5 k Each
X5990
7-27
7