XC3030A-7PC84C Xilinx Inc, XC3030A-7PC84C Datasheet - Page 26

IC LOGIC CL ARRAY 3000GAT 84PLCC

XC3030A-7PC84C

Manufacturer Part Number
XC3030A-7PC84C
Description
IC LOGIC CL ARRAY 3000GAT 84PLCC
Manufacturer
Xilinx Inc
Series
XC3000A/Lr
Datasheet

Specifications of XC3030A-7PC84C

Number Of Labs/clbs
100
Total Ram Bits
22176
Number Of I /o
74
Number Of Gates
2000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
84-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Logic Elements/cells
-
Other names
122-1018

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XC3000 Series Field Programmable Gate Arrays
Notes: 1. At power-up, V
This timing diagram shows that the EPROM requirements are extremely relaxed:
EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements.
Figure 26: Master Parallel Mode Programming Switching Characteristics
7-28
(output)
(output)
(output)
(output)
A0-A15
D0-D7
DOUT
RCLK
CCLK
RCLK
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long V
non-monotonically rising V
after V
High.
CC
To address valid
To data setup
To data hold
RCLK High
RCLK Low
has reached 4.0 V (2.5 V for the XC3000L).
CC
Product Obsolete or Under Obsolescence
must rise from 2.0 V to V
Description
CC
may require a >6- s High level on RESET, followed by a >6- s Low level on RESET and D/P
CC
min in less than 25 ms. If this is not possible, configuration can be delayed by
Address for Byte n
7 CCLKs
1
2
3
2 T
Byte
Symbol
DRC
T
T
T
T
T
DRC
RCD
RCH
RAC
RCL
Byte n - 1
D6
CC
Address for Byte n + 1
1 T
Min
600
4.0
November 9, 1998 (Version 3.1)
3 T
60
rise time of >100 ms, or a
0
0
CCLK
RAC
RCD
Max
200
D7
Units
X5380
ns
ns
ns
ns
s
R

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