IC LOGIC CL ARRAY 3000GAT 84PLCC

XC3030A-7PC84C

Manufacturer Part NumberXC3030A-7PC84C
DescriptionIC LOGIC CL ARRAY 3000GAT 84PLCC
ManufacturerXilinx Inc
SeriesXC3000A/L
XC3030A-7PC84C datasheet
 


Specifications of XC3030A-7PC84C

Number Of Labs/clbs100Total Ram Bits22176
Number Of I /o74Number Of Gates2000
Voltage - Supply4.75 V ~ 5.25 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case84-LCC (J-Lead)
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantNumber Of Logic Elements/cells-
Other names122-1018  
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Product Obsolete or Under Obsolescence
XC3000 Series Field Programmable Gate Arrays
General XC3000 Series Switching Characteristics
RESET
2 T
MR
M0/M1/M2
5 T
DONE/PROG
INIT
User State
(Output)
PWRDWN
V
(Valid)
CC
Description
M0, M1, M2 setup time required
RESET (2)
M0, M1, M2 hold time required
RESET Width (Low) req. for Abort
Width (Low) required for Re-config.
DONE/PROG
INIT response after D/P is pulled Low
PWRDWN (3) Power Down V
CC
Notes: 1. At power-up, V
must rise from 2.0 V to V
CC
holding RESET Low until Vcc has reached 4.0 V (2.5 V for XC3000L). A very long Vcc rise time of >100 ms, or a
non-monotonically rising V
may require a >1- s High level on RESET, followed by a >6- s Low level on RESET and D/P
CC
after Vcc has reached 4.0 V (2.5 V for XC3000L).
2. RESET timing relative to valid mode lines (M0, M1, M2) is relevant when RESET is used to delay configuration. The
specified hold time is caused by a shift-register filter slowing down the response to RESET during configuration.
3. PWRDWN transitions must occur while V
7-34
4 T
3 T
RM
PGW
6 T
PGI
Clear State
Symbol
2
T
MR
3
T
RM
4
T
MRW
5
T
PGW
6
T
PGI
V
CCPD
min in less than 25 ms. If this is not possible, configuration can be delayed by
CC
>4.0 V(2.5 V for XC3000L).
CC
MRW
Configuration State
Note 3
V
CCPD
X5387
Min
Max
Units
1
4.5
6
6
7
2.3
November 9, 1998 (Version 3.1)
R
s
s
s
s
s
V