IC LOGIC CL ARRAY 3000GAT 84PLCC

XC3030A-7PC84C

Manufacturer Part NumberXC3030A-7PC84C
DescriptionIC LOGIC CL ARRAY 3000GAT 84PLCC
ManufacturerXilinx Inc
SeriesXC3000A/L
XC3030A-7PC84C datasheet
 


Specifications of XC3030A-7PC84C

Number Of Labs/clbs100Total Ram Bits22176
Number Of I /o74Number Of Gates2000
Voltage - Supply4.75 V ~ 5.25 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case84-LCC (J-Lead)
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantNumber Of Logic Elements/cells-
Other names122-1018  
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Product Obsolete or Under Obsolescence
R
XC3000A CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Description
Combinatorial Delay
Logic Variables
A, B, C, D, E, to outputs X or Y
FG Mode
F and FGM Mode
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
FG Mode
F and FGM Mode
Set-up time before clock K
Logic Variables
A, B, C, D, E
FG Mode
F and FGM Mode
Data In
DI
Enable Clock
EC
Hold Time after clock K
Logic Variables
A, B, C, D, E
Data In
DI
2
Enable Clock
EC
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
1
Global Reset (RESET Pad)
RESET width (Low)
delay from RESET pad to outputs X or Y
Notes:
1. Timing is based on the XC3042A, for other devices see timing calculator.
2. The CLB K to Q output delay (T
CKO
Data In hold time requirement (T
CKDI
November 9, 1998 (Version 3.1)
XC3000 Series Field Programmable Gate Arrays
Speed Grade
Symbol
Min
1
T
ILO
8
T
CKO
T
QLO
2
T
4.5
ICK
5.0
4
T
4.0
DICK
6
T
4.5
ECCK
3
T
0
CKI
5
T
1.0
CKDI
7
T
2.0
CKEC
11
T
4.0
CH
12
T
4.0
CL
F
113.0
CLK
13
T
6.0
RPW
9
T
RIO
T
16.0
MRW
T
MRQ
, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the
, #5) of any CLB on the same die.
-7
-6
Max
Min
Max
Units
5.1
4.1
ns
5.6
4.6
ns
4.5
4.0
ns
9.5
8.0
ns
10.0
8.5
ns
3.5
ns
4.0
ns
3.0
ns
4.0
ns
0
ns
1.0
ns
2.0
ns
3.5
ns
3.5
ns
135.0
MHz
5.0
ns
6.0
5.0
ns
14.0
ns
19.0
17.0
ns
7-43
7