XC3030A-7PC44C Xilinx Inc, XC3030A-7PC44C Datasheet - Page 33

• Manufacturer Part Number: XC3030A-7PC44C
• Description: IC LOGIC CL ARRAY 3000GAT 44PLCC
• Manufacturer: Xilinx Inc
• Series: XC3000A/Lr

Specifications of XC3030A-7PC44C

• Number Of Labs/clbs: 100
• Total Ram Bits: 22176
• Number Of I /o: 34
• Number Of Gates: 2000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1017

Device Performance
The XC3000 families of FPGAs can achieve very high per-
formance. This is the result of
• A sub-micron manufacturing process, developed and
• Careful optimization of transistor geometries, circuit
• A look-up table based, coarse-grained architecture that
Actual system performance is determined by the timing of
critical paths, including the delay through the combinatorial
and sequential logic elements within CLBs and IOBs, plus
the delay in the interconnect routing. The AC-timing speci-
fications state the worst-case timing parameters for the var-
ious logic resources available in the XC3000-families
architecture.
involved in determining system performance.
Logic block performance is expressed as the propagation
time from the interconnect point at the input to the block to
the output of the block in the interconnect area. Since com-
binatorial logic is implemented with a memory lookup table
within a CLB, the combinatorial delay through the CLB,
called T
being implemented. For the combinatorial logic function
driving the data input of the storage element, the critical
timing is data set-up relative to the clock edge provided to
the flip-flop element. The delay from the clock source to the
output of the logic block is critical in the timing signals pro-
November 9, 1998 (Version 3.1)
Figure 31: Primary Block Speed Factors. Actual timing is a function of various block factors combined with routing.
factors. Overall performance can be evaluated with the timing calculator or by an optional simulation.
continuously being enhanced for the production of
state-of-the-art CMOS SRAMs.
design, and lay-out, based on years of experience with
the XC3000 family.
can collapse multiple-layer combinatorial logic into a
single function generator. One CLB can implement up
to four layers of conventional logic in as little as 1.5 ns.
CLOCK
PAD
ILO
, is always the same, regardless of the function
Figure 31
R
T
Clock to Output
PID
(K)
Product Obsolete or Under Obsolescence
T
CKO
shows a variety of elements
CLB
IOB
Combinatorial
Logic
T
ILO
CLB
XC3000 Series Field Programmable Gate Arrays
Logic
function of the number of CLB layers.
duced by storage elements. Loading of a logic-block output
is limited only by the resulting propagation delay of the
larger interconnect network. Speed performance of the
logic block is a function of supply voltage and temperature.
See
Interconnect
resources used to implement the signal path. Direct inter-
connects to the neighboring CLB provide an extremely fast
path. Local interconnects go through switch matrices
(magic boxes) and suffer an RC delay, equal to the resis-
tance of the pass transistor multiplied by the capacitance of
the driven metal line. Longlines carry the signal across the
length or breadth of the chip with only one access delay.
Generous on-chip signal buffering makes performance rel-
atively insensitive to signal fan-out; increasing fan-out from
1 to 8 changes the CLB delay by only 10%. Clocks can be
distributed with two low-skew clock distribution networks.
The tools in the Development System used to place and
route a design in an XC3000 FPGA automatically calculate
the actual maximum worst-case delays along each signal
path. This timing information can be back-annotated to the
design’s netlist for use in timing simulation or examined
with, a static timing analyzer.
Actual system performance is applications dependent. The
maximum clock rate that can be used in a system is deter-
mined by the critical path delays within that system. These
delays are combinations of incremental logic and routing
delays, and vary from design to design. In a synchronous
system, the maximum clock rate depends on the number of
combinatorial logic layers between re-synchronizing
flip-flops.
Setup
T
ICK
Figure
Figure 33
32.
performance
(K)
T
CKO
shows the achievable clock rate as a
CLB
T
OKPO
depends
IOB
T
OP
PAD
on
the
X3178
routing
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