XC3030A-7PC44C Xilinx Inc, XC3030A-7PC44C Datasheet - Page 41

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XC3030A-7PC44C

Manufacturer Part Number
XC3030A-7PC44C
Description
IC LOGIC CL ARRAY 3000GAT 44PLCC
Manufacturer
Xilinx Inc
Series
XC3000A/Lr
Datasheet

Specifications of XC3030A-7PC44C

Number Of Labs/clbs
100
Total Ram Bits
22176
Number Of I /o
34
Number Of Gates
2000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
44-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Logic Elements/cells
-
Other names
122-1017

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XC3000A CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Notes:
November 9, 1998 (Version 3.1)
Combinatorial Delay
Sequential delay
Set-up time before clock K
Hold Time after clock K
Clock
Reset Direct (RD)
Global Reset (RESET Pad)
Logic Variables
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
Logic Variables
Data In
Enable Clock
Logic Variables
Data In
Enable Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
RD width
delay from RD to outputs X or Y
RESET width (Low)
delay from RESET pad to outputs X or Y
1. Timing is based on the XC3042A, for other devices see timing calculator.
2. The CLB K to Q output delay (T
Data In hold time requirement (T
R
Description
Product Obsolete or Under Obsolescence
A, B, C, D, E, to outputs X or Y
FG Mode
F and FGM Mode
FG Mode
F and FGM Mode
A, B, C, D, E
FG Mode
F and FGM Mode
DI
EC
A, B, C, D, E
DI
EC
2
1
CKO
CKDI
, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the
, #5) of any CLB on the same die.
XC3000 Series Field Programmable Gate Arrays
11
12
13
1
8
2
4
6
3
5
7
9
Speed Grade
Symbol
T
T
T
T
T
T
T
T
T
F
T
T
T
T
T
ECCK
CKEC
T
DICK
CKDI
MRW
CKO
RPW
MRQ
QLO
CLK
ICK
CKI
RIO
ILO
CH
CL
113.0
16.0
Min
4.5
5.0
4.0
4.5
1.0
2.0
4.0
4.0
6.0
0
-7
Max
10.0
19.0
5.1
5.6
4.5
9.5
6.0
135.0
14.0
Min
3.5
4.0
3.0
4.0
1.0
2.0
3.5
3.5
5.0
0
-6
Max
17.0
4.1
4.6
4.0
8.0
8.5
5.0
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7-43
7

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