XC3030L-8VQ64C Xilinx Inc, XC3030L-8VQ64C Datasheet - Page 15

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XC3030L-8VQ64C

Manufacturer Part Number
XC3030L-8VQ64C
Description
IC FPGA C-TEMP 3.3V 64-VQFP
Manufacturer
Xilinx Inc
Series
XC3000A/Lr
Datasheet

Specifications of XC3030L-8VQ64C

Number Of Labs/clbs
100
Total Ram Bits
22176
Number Of I /o
54
Number Of Gates
2000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Logic Elements/cells
-

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A buffer in the upper left corner of the FPGA chip drives a
global net which is available to all K inputs of logic blocks.
Using the global buffer for a clock signal provides a
skew-free, high fan-out, synchronized clock for use at any
or all of the IOBs and CLBs. Configuration bits for the K
input to each logic block can select this global line or
another routing resource as the clock source for its
flip-flops. This net may also be programmed to drive the die
edge clock lines for IOB use. An enhanced speed, CMOS
threshold, direct access to this buffer is available at the sec-
ond pad from the top of the left die edge.
A buffer in the lower right corner of the array drives a hori-
zontal Longline that can drive programmed connections to
a vertical Longline in each interconnection column. This
alternate buffer also has low skew and high fan-out. The
network formed by this alternate buffer’s Longlines can be
selected to drive the K inputs of the CLBs. CMOS thresh-
old, high speed access to this buffer is available from the
third pad from the bottom of the right die edge.
Internal Busses
A pair of 3-state buffers, located adjacent to each CLB, per-
mits logic to drive the horizontal Longlines. Logic operation
November 9, 1998 (Version 3.1)
Figure 18: Design Editor.
An extra large view of possible interconnections in the lower right corner of the XC3020A.
R
INTERCONNECT
BIDIRECTIONAL
Product Obsolete or Under Obsolescence
BUFFERS
P40
GG
HG
P41
GLOBAL NET
P42
GH
HH
3 VERTICAL LONG
LINES PER COLUMN
XC3000 Series Field Programmable Gate Arrays
P43
OS
C
of the 3-state buffer controls allows them to implement wide
multiplexing functions. Any 3-state buffer input can be
selected as drive for the horizontal long-line bus by apply-
ing a Low logic level on its 3-state control line. See
Figure
can result from multiple drivers with opposing logic levels.
Control of the 3-state input by the same signal that drives
the buffer input, creates an open-drain wired-AND function.
A logic High on both buffer inputs creates a high imped-
ance, which represents no contention. A logic Low enables
the buffer to drive the Longline Low. See
resistors are available at each end of the Longline to pro-
vide a High output when all connected buffers are non-con-
ducting. This forms fast, wide gating functions. When data
drives the inputs, and separate signals drive the 3-state
control lines, these buffers form multiplexers (3-state bus-
ses). In this case, care must be used to prevent contention
through multiple active buffers of conflicting levels on a
common line. Each horizontal Longline is also driven by a
weak keeper circuit that prevents undefined floating levels
by maintaining the previous logic level when the line is not
driven by an active buffer or a pull-up resistor.
shows 3-state buffers, Longlines and pull-up resistors.
16. The user is required to avoid contention which
RST
.l
.q
.Q
P48
P47
BCL
KIN
P46
D
P
G
M
.ck
.lk
I/O CLOCKS
HORIZONTAL LONG LINE
OSCILLATOR
AMPLIFIER OUTPUT
DIRECTINPUT OF P47
TO AUXILIARY BUFFER
CRYSTAL OSCILLATOR
BUFFER
3-STATE CONTROL
HORIZONTAL LONG LINE
PULL-UP RESISTOR
3-STATE INPUT
3-STATE BUFFER
ALTERNATE BUFFER
X1245
Figure
17. Pull-up
Figure 18
7-17
7

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