XC3030L-8VQ64C Xilinx Inc, XC3030L-8VQ64C Datasheet - Page 28

• Manufacturer Part Number: XC3030L-8VQ64C
• Description: IC FPGA C-TEMP 3.3V 64-VQFP
• Manufacturer: Xilinx Inc
• Series: XC3000A/Lr

Specifications of XC3030L-8VQ64C

• Number Of Labs/clbs: 100
• Total Ram Bits: 22176
• Number Of I /o: 54
• Number Of Gates: 2000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -

XC3000 Series Field Programmable Gate Arrays
Notes: 1. At power-up, V
Note:
will go active within 60 ns after the end of WS. BUSY will stay active for several microseconds. WS may be asserted
immediately after the end of BUSY.
Figure 28: Peripheral Mode Programming Switching Characteristics
7-30
WS, CS0, CS1
WRITE
RDY
This timing diagram shows very relaxed requirements: Data need not be held beyond the rising edge of WS. BUSY
RDY/BUSY
2. Configuration must be delayed until the INIT of all FPGAs is High.
3. Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and the
4. CCLK and DOUT timing is tested in slave mode.
5. T
holding RESET Low until V
non-monotonically rising V
after V
phase of the internal timing generator for CCLK.
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is
loaded into the input register before the second-level buffer has started shifting out data.
D0-D7
DOUT
CCLK
BUSY
CS2
CC
indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest T
Effective Write time required
(Assertion of CS0, CS1, CS2, WS)
DIN Setup time required
DIN Hold time required
RDY/BUSY delay after end of WS
Earliest next WS after end of BUSY
BUSY Low time generated
has reached 4.0 V (2.5 V for the XC3000L).
CC
Product Obsolete or Under Obsolescence
must rise from 2.0 V to V
WRITE TO FPGA
Description
CC
CC
T
CA
may require a >6- s High level on RESET, followed by a >6- s Low level on RESET and D/P
has reached 4.0 V (2.5 V for the XC3000L). A very long V
4
1
2
T
Valid
T
DC
WTRB
CC
min in less than 25 ms. If this is not possible, configuration can be delayed by
T
CD
3
1
2
3
4
5
6
T
BUSY
D6
Symbol
6
Previous Byte
T
T
T
T
T
T
WTRB
RBWT
BUSY
CA
DC
CD
D7
CC
Min
100
2.5
rise time of >100 ms, or a
November 9, 1998 (Version 3.1)
60
0
0
D0
Max
60
D1
9
New Byte
D2
periods
CCLK
Units
BUSY
X5992
ns
ns
ns
ns
ns
R