XC4005E-3PC84I | |
|---|---|
| Manufacturer Part Number | XC4005E-3PC84I |
| Description | IC FPGA I-TEMP 5V 3-SPD 84-PLCC |
| Manufacturer | Xilinx Inc |
| Series | XC4000E/X |
| XC4005E-3PC84I datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
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Specifications of XC4005E-3PC84I | |||
|---|---|---|---|
| Number Of Logic Elements/cells | 466 | Number Of Labs/clbs | 196 |
| Total Ram Bits | 6272 | Number Of I /o | 61 |
| Number Of Gates | 5000 | Voltage - Supply | 4.5 V ~ 5.5 V |
| Mounting Type | Surface Mount | Operating Temperature | -40°C ~ 100°C |
| Package / Case | 84-LCC (J-Lead) | Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant |
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Product Obsolete or Under Obsolescence
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Write to LCA
WS/CS0
RS, CS1
1 T
CA
2 T
DC
D0-D7
CCLK
4
T
WTRB
RDY/BUSY
DOUT
Description
Effective Write time
(CS0, WS=Low; RS, CS1=High)
Write
DIN setup time
DIN hold time
RDY/BUSY delay after end of
Write or Read
RDY
RDY/BUSY active after beginning
of Read
RDY/BUSY Low output (Note 4)
Notes: 1. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte
processing and the phase of the internal timing generator for CCLK.
3. CCLK and DOUT timing is tested in slave mode.
4. T
indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest
BUSY
T
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest T
BUSY
is loaded into the input register before the second-level buffer has started shifting out data
This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of
go active within 60 ns after the end of
may not be terminated until RDY/
BUSY
Figure 59: Asynchronous Peripheral Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6)
3 T
CD
6 T
BUSY
Previous Byte D6
D7
Symbol
1
T
CA
2
T
DC
3
T
CD
4
T
WTRB
7
6
T
BUSY
. A new write may be asserted immediately after RDY/
WS
has been High for one CCLK period.
Read Status
RS, CS0
WS, CS1
4
7
READY
D7
BUSY
D0
D1
D2
Min
Max
Units
100
ns
60
ns
0
ns
60
ns
60
ns
2
9
CCLK
periods
occurs when a new word
BUSY
. RDY/
WS
BUSY
goes Low, but write
BUSY
X6097
6
will
6-67
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