XC4005E-3PC84I | |
|---|---|
| Manufacturer Part Number | XC4005E-3PC84I |
| Description | IC FPGA I-TEMP 5V 3-SPD 84-PLCC |
| Manufacturer | Xilinx Inc |
| Series | XC4000E/X |
| XC4005E-3PC84I datasheets |
|
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Specifications of XC4005E-3PC84I | |||
|---|---|---|---|
| Number Of Logic Elements/cells | 466 | Number Of Labs/clbs | 196 |
| Total Ram Bits | 6272 | Number Of I /o | 61 |
| Number Of Gates | 5000 | Voltage - Supply | 4.5 V ~ 5.5 V |
| Mounting Type | Surface Mount | Operating Temperature | -40°C ~ 100°C |
| Package / Case | 84-LCC (J-Lead) | Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant |
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PrevNext
Product Obsolete or Under Obsolescence
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
tions of the CLB, with the exception of the redefinition of the
control signals. In 16x2 and 16x1 modes, the H’ function
generator can be used to implement Boolean functions of
F’, G’, and D1, and the D flip-flops can latch the F’, G’, H’, or
D0 signals.
Single-Port Edge-Triggered Mode
Edge-triggered (synchronous) RAM simplifies timing
requirements. XC4000 Series edge-triggered RAM timing
operates like writing to a data register. Data and address
are presented. The register is enabled for writing by a logic
High on the write enable input, WE. Then a rising or falling
clock edge loads the data into the register, as shown in
Figure
3.
WCLK (K)
T
WSS
WE
T
DSS
DATA IN
T
ASS
ADDRESS
T
ILO
DATA OUT
OLD
Figure 3:
Edge-Triggered RAM Write Timing
Complex timing relationships between address, data, and
write enable signals are not required, and the external write
enable pulse becomes a simple clock enable. The active
edge of WCLK latches the address, input data, and WE sig-
May 14, 1999 (Version 1.6)
nals. An internal write pulse is generated that performs the
write. See
Figure 4
CLB configured as 16x2 and 32x1 edge-triggered, sin-
gle-port RAM.
The relationships between CLB pins and RAM inputs and
outputs for single-port, edge-triggered mode are shown in
Table
5.
The Write Clock input (WCLK) can be configured as active
on either the rising edge (default) or the falling edge. It uses
the same CLB pin (K) used to clock the CLB flip-flops, but it
can be independently inverted. Consequently, the RAM
output can optionally be registered within the same CLB
either by the same clock edge as the RAM, or by the oppo-
site edge of this clock. The sense of WCLK applies to both
T
function generators in the CLB when both are configured
WPS
as RAM.
The WE pin is active-High and is not invertible within the
T
WHS
CLB.
Note: The pulse following the active edge of WCLK (T
in
Figure
3) must be less than one millisecond wide. For
T
DHS
most applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this
point in the write cycle could result in excessive current and
T
even damage to the larger devices if many CLBs are con-
AHS
figured as edge-triggered RAM.
Table 5: Single-Port Edge-Triggered RAM Signals
T
ILO
RAM Signal
T
WOS
D
NEW
A[3:0]
X6461
A[4]
WE
WCLK
SPO
(Data Out)
and
Figure 5
for block diagrams of a
WPS
CLB Pin
Function
D0 or D1 (16x2,
Data In
16x1), D0 (32x1)
F1-F4 or G1-G4
Address
D1 (32x1)
Address
WE
Write Enable
K
Clock
F’ or G’
Single Port Out
(Data Out)
6-13
6
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