XC4020XL-09BG256C Xilinx Inc, XC4020XL-09BG256C Datasheet
XC4020XL-09BG256C
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R May 14, 1999 (Version 1.6) XC4000E and XC4000X Series Features Note: Information in this data sheet covers the XC4000E, XC4000EX, and XC4000XL families. A separate data sheet covers the XC4000XLA and XC4000XV families. Electrical Specifications and package/pin information are ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays Table 1: XC4000E and XC4000X Series Field Programmable Gate Arrays Max Logic Logic Gates Device Cells (No RAM) XC4002XL 152 1,600 XC4003E 238 3,000 XC4005E/XL 466 5,000 XC4006E 608 6,000 XC4008E 770 ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E and XC4000X Series Compared to the XC4000 For readers already familiar with the XC4000 family of Xil- inx Field Programmable Gate Arrays, the major new fea- tures in the XC4000 ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays Input Thresholds The input thresholds of 5V devices can be globally config- ured for either TTL (1.2 V threshold) or CMOS (2.5 V threshold), just like XC2000 and XC3000 inputs. The two ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays Detailed Functional Description XC4000 Series devices achieve high speed through advanced semiconductor technology and improved archi- tecture. The XC4000E and XC4000X support system clock rates MHz and ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays • • • LOGIC FUNCTION G1- LOGIC FUNCTION F1-F4 ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays Set/Reset An asynchronous storage element input (SR) can be con- figured as either set or reset. This configuration option determines the state in which each flip-flop becomes oper- ational after configuration. ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays Supported CLB memory configurations and timing modes for single- and dual-port modes are shown in XC4000 Series devices are the first programmable logic devices with edge-triggered (synchronous) and dual-port RAM accessible to ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays tions of the CLB, with the exception of the redefinition of the control signals. In 16x2 and 16x1 modes, the H’ function generator can be used to implement Boolean functions of ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays • • • • • • • • • (CLOCK) Figure 4: 16x2 (or 16x1) Edge-Triggered ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays Dual-Port Edge-Triggered Mode In dual-port mode, both the F and G function generators are used to create a single 16x1 RAM array with one write port and two read ports. The ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays • • • • • • • • • (CLOCK) Figure 7: 16x1 Edge-Triggered Dual-Port ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays • • • • • • • • • X6746 Figure 9: 16x2 (or 16x1) ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays Fast Carry Logic Each CLB F and G function generator contains dedicated arithmetic logic for the fast generation of carry and borrow signals. This extra output is passed on to the function ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays C C OUT IN DOWN CARRY LOGIC G CARRY OUT0 H1 F CARRY OUT Figure 13: Fast Carry ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays X2000 Figure 14: Detail of XC4000E Dedicated Carry Logic Input/Output Blocks (IOBs) User-configurable input/output blocks (IOBs) provide the interface between external package pins ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays T Out Output Clock Clock Enable Input Clock Figure 15: Simplified Block Diagram of XC4000E IOB T Out Output Clock Clock Enable Input ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays Table 8: Supported Sources for XC4000 Series Device Inputs XC4000E/EX Series Inputs Source 5 V, TTL Any device, Vcc = 3.3 V, CMOS outputs XC4000 Series, Vcc = 5 V, TTL outputs ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays Additional Input Latch for Fast Capture (XC4000X only) The XC4000X IOB has an additional optional latch on the input. This latch, as shown in Figure 16, is clocked by the output ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays Any XC4000 Series 5-Volt device with its outputs config- ured in TTL mode can drive the inputs of any typical 3.3-Volt device. (For a detailed discussion of how to inter- face between ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays Output Multiplexer/2-Input Function Generator (XC4000X only) As shown in Figure 16 on page 21, the output path in the XC4000X IOB contains an additional multiplexer not avail- able in the XC4000E ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays or clear on reset and after configuration. Other than the glo- bal GSR net, no user-controlled set/reset signal is available to the I/O flip-flops. The choice of set or clear applies to ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays ~100 k "Weak Keeper" Figure 22: 3-State Buffers Implement a Multiplexer Wide Edge Decoders Dedicated decoder circuitry boosts the performance of wide decoding functions. When the address or data field is ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays The oscillator output is optionally available after configura- tion. Any two of four resynchronized taps of a built-in divider are also available. These taps are at the fourth, ninth, four- teenth and ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays Quad Long Global Clock Figure 25: High-Level Routing Diagram of XC4000 Series CLB (shaded arrows indicate XC4000X only) Table 14: Routing per CLB in XC4000 Series Devices XC4000E Vertical Horizontal Vertical ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays Common to XC4000E and XC4000X XC4000X only Programmable Switch Matrix Figure 27: Detail of Programmable Interconnect Associated with XC4000 Series CLB 6-30 R QUAD DOUBLE SINGLE DOUBLE LONG ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays CLB CLB PSM PSM CLB CLB PSM PSM CLB CLB Figure 28: Single- and Double-Length Lines, with Programmable Switch Matrices (PSMs) Double-Length Lines The double-length lines consist of a grid of ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays circuit prevents undefined floating levels. However overridden by any driver, even a pull-up resistor. Each XC4000E longline has a programmable splitter switch at its center, as does each XC4000X longline ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays WED IOB WED IOB WED Direct Connect Figure 31: High-Level Routing Diagram of XC4000 Series VersaRing (Left Edge) WED = Wide Edge Decoder, IOB = I/O Block (shaded arrows indicate XC4000X ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays Common to XC4000E and XC4000X XC4000X only Figure 33: Detail of Programmable Interconnect Associated with XC4000 Series IOB (Left Edge) 6-34 IOB IOB T O ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays IOB inputs and outputs interface with the octal lines via the single-length interconnect lines. Single-length lines are also used for communication between the octals and dou- ble-length lines, quads, and longlines ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays BUFGS PGCK1 SGCK1 BUFGP 4 IOB locals Any BUFGS X4 locals One BUFGP per Global Line IOB BUFGS PGCK2 SGCK2 BUFGP Figure 34: XC4000E Global Net Distribution BUFGLS GCK1 GCK8 BUFGE BUFGLS ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays Global Nets and Buffers (XC4000X only) Eight vertical longlines in each CLB column are driven by special global buffers. These longlines are in addition to the vertical longlines used for standard ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays 8 IOB CLB CLB B I CLB CLB IOB 3 Figure 36: Any BUFGLS (GCK1 - GCK8) Can Drive Any or All Clock Inputs on the ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays The top and bottom Global Early buffers are about 1 ns slower clock to out than the left and right Global Early buff- ers. The Global Early buffers can be driven ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays Table 16: Pin Descriptions I/O I/O During After Pin Name Config. Config. Permanently Dedicated Pins Eight or more (depending on package) connections to the nominal +5 V supply voltage VCC I I ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays Table 16: Pin Descriptions (Continued) I/O I/O During After Pin Name Config. Config. If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select inputs ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays Table 16: Pin Descriptions (Continued) I/O I/O During After Pin Name Config. Config. These four inputs are used in Asynchronous Peripheral mode. The chip is selected when CS0 is Low and CS1 ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays Figure 41 on page diagram of the XC4000 Series boundary scan logic. It includes three bits of Data Register per IOB, the IEEE 1149.1 Test Access Port controller, ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB BYPASS REGISTER INSTRUCTION REGISTER TDI Figure 41: XC4000 Series Boundary Scan Logic Instruction Set The XC4000 Series boundary scan instruction set ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays Table 17: Boundary Scan Instructions Instruction I2 Test TDO Source I1 I0 Selected EXTEST SAMPLE/PR DR ELOAD USER 1 BSCAN. TDO1 ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays Configuration Modes XC4000E devices have six configuration modes. XC4000X devices have the same six modes, plus an additional con- figuration mode. These modes are selected by a 3-bit input code applied to ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays is passed through and is captured by each FPGA when it recognizes the 0010 preamble. Following the length-count data, each FPGA outputs a High on DOUT until it has received its ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays Setting CCLK Frequency For Master modes, CCLK can be generated in either of two frequencies. In the default slow mode, the frequency ranges from 0.5 MHz to 1.25 MHz for XC4000E and ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays Table 20: XC4000E Program Data Device XC4003E XC4005E Max Logic Gates 3,000 5,000 CLBs 100 196 (Row x Col.) (10 x 10) (14 x 14) IOBs 80 112 Flip-Flops 360 616 ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays used), and if RAM is present, the RAM content must be unchanged. Statistically, one error out of 2048 might go undetected. Configuration Sequence There are four major steps in the XC4000 Series ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays Low. During this time delay long as the PROGRAM input is asserted, the configuration logic is held in a Config- uration Memory Clear state. The configuration-memory frames are consecutively ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays The default option, and the most practical one, is for DONE to go High first, disconnecting the configuration data source and avoiding any contention when the I/Os become active one clock later. ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays Length Count Match CCLK DONE I/O XC2000 Global Reset DONE XC3000 I/O Global Reset DONE I/O XC4000E/X CCLK_NOSYNC GSR Active DONE IN DONE C1 I/O XC4000E/X CCLK_SYNC GSR ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays Start-up from a User Clock (STARTUP.CLK) When, instead of CCLK, a user-supplied start-up clock is selected used to bridge the unknown phase relation- ship between CCLK and the user clock. ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays Q3 Q1/Q4 STARTUP DONE FULL LENGTH COUNT K CLEAR MEMORY CCLK 0 STARTUP.CLK 1 USER NET ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays IF UNCONNECTED, DEFAULT IS CCLK READ_TRIGGER MD0 Figure 49: Readback Schematic Example Readback Options Readback options are: Read Capture, Read Abort, and Clock Select. They are set with the bitstream generation software. ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E/EX/XL Program Readback Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays Table 22: Pin Functions During Configuration CONFIGURATION MODE <M2:M1:M0> SLAVE MASTER SERIAL SERIAL PERIPHERAL <1:1:1> <0:0:0> M2(HIGH) (I) M2(LOW) (I) M2(LOW) (I) M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) M0(HIGH) (I) M0(LOW) (I) ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays Table 23: Pin Functions During Configuration CONFIGURATION MODE <M2:M1:M0> SLAVE MASTER SYNCH. SERIAL SERIAL PERIPHERAL <1:1:1> <0:0:0> <0:1:1> M2(HIGH) (I) M2(LOW) (I) M2(LOW) (I) M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) M0(HIGH) ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays Configuration Timing The seven configuration modes are discussed in detail in this section. Timing specifications are included. Slave Serial Mode In Slave Serial mode, an external signal drives the CCLK input of ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays Master Serial Mode In Master Serial mode, the CCLK output of the lead FPGA drives a Xilinx Serial PROM that feeds the FPGA DIN input. Each rising edge of the CCLK ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays Master Parallel Modes In the two Master Parallel modes, the lead FPGA directly addresses an industry-standard byte-wide EPROM, and accepts eight data bits just before incrementing or decre- menting the address outputs. ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays A0-A17 (output) D0-D7 RCLK (output) CCLK (output) DOUT (output) Description Delay to Address valid RCLK Data setup time Data hold time Notes power-up, Vcc must rise from 2.0 V ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays Synchronous Peripheral Mode Synchronous Peripheral mode can also be considered Slave Parallel mode. An external signal drives the CCLK input(s) of the FPGA(s). The first byte of parallel configura- tion data must ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays CCLK INIT BYTE 0 DOUT RDY/BUSY Description INIT (High) setup time setup time hold time CCLK CCLK High time CCLK Low time CCLK Frequency Notes: ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays Asynchronous Peripheral Mode Write to FPGA Asynchronous Peripheral mode uses the trailing edge of the logic AND condition of WS and CS0 being Low and RS and CS1 being High to accept ...
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R XC4000E and XC4000X Series Field Programmable Gate Arrays Write to LCA WS/CS0 RS, CS1 D0-D7 CCLK 4 T WTRB RDY/BUSY DOUT Description Effective Write time (CS0, WS=Low; RS, CS1=High) Write DIN setup time ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays Configuration Switching Characteristics T Vcc PROGRAM INIT CCLK OUTPUT or INPUT X1532 Master Modes (XC4000E/EX) Description Power-On Reset Program Latency CCLK (output) Delay CCLK (output) Period, slow CCLK (output) Period, fast Master ...
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... XC4005XL - -09C XC4010XL - -09C XC4013XL - -09C -08C - XC4020XL - -09C -3 -2 XC4028XL -1 -09C -3 -2 XC4036XL -1 -09C -08C -3 -2 XC4044XL -1 -09C -3 -2 XC4052XL -1 -09C -3 -2 XC4062XL -1 -09C -08C -3 -2 XC4085XL -1 -09C 1/29/ Commercial + Industrial +100 C J May 14, 1999 (Version 1.6) LINX at http://www.xilinx.com for the latest revision of ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays Table 25: Component Availability Chart for XC4000E FPGAs PINS 84 100 100 TYPE CODE - XC4003E - ...
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... Max Device I/O XC4002XL XC4005XL 112 112 XC4010XL 160 61 77 113 XC4013XL 192 113 XC4020XL 224 113 XC4028XL 256 XC4036XL 288 XC4044XL 320 XC4052XL 352 XC4062XL 384 XC4085XL 448 1/29/99 Table 28: User I/O Chart for XC4000E FPGAs Max Device I/O XC4003E 80 ...
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XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000 Series Electrical Characteristics and Device-Specific Pinout Table For the latest Electrical Characteristics and package/pinout information for each XC4000 Family, see the Xilinx web site at http://www.xilinx.com/partinfo/databook.htm#xc4000 Ordering Information Example: Device Type ...