CY7C64713-128AXC Cypress Semiconductor Corp, CY7C64713-128AXC Datasheet

IC MCU USB EZ FX1 16KB 128LQFP

CY7C64713-128AXC

Manufacturer Part Number
CY7C64713-128AXC
Description
IC MCU USB EZ FX1 16KB 128LQFP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB FX1™r
Datasheet

Specifications of CY7C64713-128AXC

Program Memory Type
ROMless
Package / Case
128-LQFP
Applications
USB Microcontroller
Core Processor
8051
Controller Series
CY7C647xx
Ram Size
16K x 8
Interface
I²C, USB, USART
Number Of I /o
40
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Processor Series
CY7C64xx
Core
M8C
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C/USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
40
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
CY3674
Minimum Operating Temperature
0 C
Cpu Family
FX2LP
Device Core
8051
Device Core Size
8b
Frequency (max)
48MHz
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
40
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.45V
Operating Supply Voltage (min)
3.15V
Instruction Set Architecture
CISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
128
Package Type
TQFP
Controller Family/series
(8051) USB
Core Size
8 Bit
No. Of I/o's
40
Ram Memory Size
16KB
Cpu Speed
48MHz
No. Of Timers
3
Embedded Interface Type
I2C, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
428-1681 - KIT USB FX1 DEVELOPMENT BOARD428-1677 - KIT DEVELOPMENT EZ-USB FX2LP428-1339 - KIT LOW SPEED PERSONALITY BOARD
Lead Free Status / Rohs Status
Compliant
Other names
428-1678
CY7C64713-128AXC

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Features
Cypress Semiconductor Corporation
Document #: 38-08039 Rev. *F
Single Chip Integrated USB Transceiver, SIE, and Enhanced
8051 Microprocessor
Fit, Form, and Function Upgradable to the FX2LP
(CY7C68013A)
Draws No More than 65 mA in Any Mode, Making the FX1
Suitable for Bus Powered Applications
Software: 8051 Runs from Internal RAM, which is:
16 KBytes of On-Chip Code/Data RAM
Four Programmable BULK/INTERRUPT/ISOCHRONOUS
Endpoints
Additional Programmable (BULK/INTERRUPT) 64-byte
Endpoint
8- or 16-bit External Data Interface
Smart Media Standard ECC Generation
GPIF
Pin compatible
Object code compatible
Functionally compatible (FX1 functionality is a Subset of the
FX2LP)
Downloaded using USB
Loaded from EEPROM
External memory device (128 pin configuration only)
Buffering options: double, triple, and quad
Allows direct connection to most parallel interfaces; 8- and
16-bit
Programmable waveform descriptors and configuration
registers to define waveforms
Supports multiple Ready (RDY) inputs and Control (CTL)
outputs
198 Champion Court
Full Speed USB Peripheral Controller
EZ-USB FX1™ USB Microcontroller
Integrated, Industry Standard 8051 with Enhanced Features:
3.3V Operation with 5V Tolerant Inputs
Smart SIE
Vectored USB Interrupts
Separate Data Buffers for the Setup and DATA Portions of a
CONTROL Transfer
Integrated I
48 MHz, 24 MHz, or 12 MHz 8051 Operation
Four Integrated FIFOs
Vectored for FIFO and GPIF Interrupts
Up to 40 General Purpose IOs (GPIO)
Four Package Options:
Up to 48 MHz clock rate
Four clocks for each instruction cycle
Two USARTS
Three counters or timers
Expanded interrupt system
Two data pointers
Brings glue and FIFOs inside for lower system cost
Automatic conversion to and from 16-bit buses
Master or slave operation
FIFOs can use externally supplied clock or asynchronous
strobes
Easy interface to ASIC and DSP ICs
128 pin TQFP
100 pin TQFP
56 pin SSOP
56 pin QFN Pb-free
San Jose
2
C Controller, Running at 100 or 400 KHz
,
CA 95134-1709
Revised May 22, 2009
CY7C64713
408-943-2600
[+] Feedback

Related parts for CY7C64713-128AXC

CY7C64713-128AXC Summary of contents

Page 1

... Vectored for FIFO and GPIF Interrupts ■ General Purpose IOs (GPIO) ■ Four Package Options: ■ 128 pin TQFP ❐ 100 pin TQFP ❐ 56 pin SSOP ❐ 56 pin QFN Pb-free ❐ • 198 Champion Court • San Jose CY7C64713 , CA 95134-1709 • 408-943-2600 Revised May 22, 2009 [+] Feedback ...

Page 2

... MHz, four clocks/cycle Additional IOs (24 RAM ECC Smart USB Engine ‘Soft Configuration’ FIFO and endpoint memory Easy firmware changes (master or slave operation) CY7C64713 Master Abundant I/O including two USARTS General ADDR (9) programmable I/F to ASIC/DSP or bus GPIF standards such as RDY (6) ATAPI, EPP, etc ...

Page 3

... Functional Description EZ-USB FX1™ (CY7C64713 full speed, highly integrated, USB microcontroller. By integrating the USB transceiver, Serial Interface Engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very cost effective solution that provides superior time-to-market advantages. ...

Page 4

... USB specification. Interrupt System INT2 Interrupt Request and Enable Registers FX1 implements an autovector feature for INT2 and INT4. There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF) vectors. See EZ-USB Technical Reference Manual details. CY7C64713 SCON1 PSW ACC ...

Page 5

... EP8 OUT was Pinged and it NAK’d Bus errors exceeded the programmed limit Reserved Reserved ISO EP2 OUT PID sequence error ISO EP4 OUT PID sequence error ISO EP6 OUT PID sequence error ISO EP8 OUT PID sequence error CY7C64713 Table 4 on page Notes Page [+] Feedback ...

Page 6

... RESET# VCC T RESET Power on Reset Note 3. If the external clock is powered at the same time as the CY7C64713 and has a stabilization wait period. It must be added to the 200 μs. Document #: 38-08039 Rev. *F Source Endpoint 2 Programmable Flag Endpoint 4 Programmable Flag Endpoint 6 Programmable Flag Endpoint 8 Programmable Flag ...

Page 7

... KBytes RAM here—RD#/WR# memory here— Code and Data strobes are not PSEN# strobe (PSEN#,RD#,WR#)* active) is not active) Data 2 *SUDPTR, USB upload/download interface boot access CY7C64713 48 KBytes External Code Memory (PSEN#) Code Page [+] Feedback ...

Page 8

... E740 E73F 64 Bytes RESERVED E700 E6FF 8051 Addressable Registers (512) E500 E4FF Reserved (128) E480 E47F 128 bytes GPIF Waveforms E400 E3FF Reserved (512) E200 E1FF 512 bytes 8051 xdata RAM E000 CY7C64713 64 KBytes External Code Memory (PSEN#) Code Page [+] Feedback ...

Page 9

... EP8 EP8 1023 1023 CY7C64713 bulk 64 int 64 int 64 bulk 64 int 64 int 64 bulk out (2×) 64 int out (2×) 64 iso out (2×) 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×) 64 bulk in (2×) 64 int in (2×) 64 iso in (2×) 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×) on page 9 ...

Page 10

... GPIF The GPIF is a flexible 8 or 16-bit parallel interface driven by a user programmable finite state machine. It allows the CY7C64713 to perform local bus mastering, and can implement a wide variety of protocols such as ATA interface, printer parallel port, and Utopia. The GPIF has six programmable control outputs (CTL), nine address outputs (GPIFADRx), and six general purpose Ready inputs (RDY) ...

Page 11

... WR#, are present in the 100 pin version. In the 100 pin and 0 0 128 pin versions, an 8051 control bit is set to pulse the RD# and 0 1 WR# pins when the 8051 reads from and writes to the PORTC CY7C64713 2 C interface boot loader loads the 2 C bus using 2 C master control 2 C slave. Figure 7 on ...

Page 12

... INT5 RD# WR# CS# OE# PSEN# A15 A14 A13 A12 A11 A10 128 CY7C64713 Slave FIFO FD[15] FD[14] FD[13] FD[12] FD[11] FD[10] FD[9] FD[8] FD[7] FD[6] FD[5] FD[4] FD[3] FD[2] FD[1] FD[0] SLRD SLWR FLAGA FLAGB FLAGC INT0#/ PA0 INT1#/ PA1 SLOE WU2/PA3 ...

Page 13

... Figure 8. CY7C64713 128 pin TQFP Pin Assignment CLKOUT 1 VCC 2 GND 3 RDY0/*SLRD 4 RDY1/*SLWR 5 RDY2 6 RDY3 7 RDY4 8 RDY5 9 AVCC 10 XTALOUT 11 XTALIN 12 AGND AVCC 17 DPLUS 18 DMINUS 19 AGND 20 A11 21 A12 22 A13 23 A14 24 A15 25 VCC 26 GND 27 INT4 *IFCLK 32 RESERVED 33 BKPT SCL 36 SDA 37 OE# 38 Document #: 38-08039 Rev. *F ...

Page 14

... Figure 9. CY7C64713 100 pin TQFP Pin Assignment VCC 1 GND 2 RDY0/*SLRD 3 RDY1/*SLWR 4 RDY2 5 RDY3 6 RDY4 7 RDY5 8 AVCC 9 XTALOUT 10 XTALIN 11 AGND AVCC 16 DPLUS 17 DMINUS 18 AGND 19 VCC 20 GND 21 INT4 *IFCLK 26 RESERVED 27 BKPT 28 SCL 29 SDA 30 Document #: 38-08039 Rev. *F PA7/*FLAGD/SLCS# PA6/*PKTEND PA5/FIFOADR1 ...

Page 15

... Figure 10. CY7C64713 56 pin SSOP Pin Assignment Document #: 38-08039 Rev. *F CY7C64713 56 pin SSOP PD5/FD13 PD4/FD12 PD6/FD14 PD3/FD11 PD7/FD15 PD2/FD10 GND PD1/FD9 CLKOUT PD0/FD8 VCC *WAKEUP GND VCC RDY0/*SLRD RESET# RDY1/*SLWR GND AVCC PA7/*FLAGD/SLCS# XTALOUT PA6/PKTEND XTALIN PA5/FIFOADR1 AGND PA4/FIFOADR0 ...

Page 16

... Figure 11. CY7C64713 56 pin QFN Pin Assignment RDY0/*SLRD 1 RDY1/*SLWR 2 AVCC 3 XTALOUT 4 XTALIN 5 AGND 6 AVCC 7 DPLUS 8 DMINUS 9 AGND 10 VCC 11 GND 12 *IFCLK 13 RESERVED 14 Document #: 38-08039 Rev CY7C64713 36 56 pin QFN CY7C64713 RESET# GND PA7/*FLAGD/SLCS# PA6/*PKTEND PA5/FIFOADR1 PA4/FIFOADR0 PA3/*WU2 PA2/*SLOE ...

Page 17

... CY7C64713 Pin Definitions The FX1 Pin Definitions for CY7C64713 follow. Table 8. FX1 Pin Definitions 128 100 56 56 Name TQFP TQFP SSOP QFN AVCC AVCC AGND AGND DMINUS DPLUS 117 A4 118 A5 119 A6 120 A7 126 A8 127 A9 128 A10 21 A11 22 A12 23 A13 24 A14 25 A15 ...

Page 18

... FIFOADR0 is an input-only address select for the slave FIFOs connected to FD[7..0] or FD[15..0]. I/O/Z I Multiplexed pin whose function is selected by: (PA5) IFCONFIG[1..0]. PA5 is a bidirectional I/O port pin. FIFOADR1 is an input-only address select for the slave FIFOs connected to FD[7..0] or FD[15..0]. CY7C64713 Description “Reset and Page [+] Feedback ...

Page 19

... Multiplexed pin whose function is selected by PORTCCFG.1 (PC1) PC1 is a bidirectional I/O port pin. GPIFADR1 is a GPIF address output pin. I/O/Z I Multiplexed pin whose function is selected by PORTCCFG.2 (PC2) PC2 is a bidirectional I/O port pin. GPIFADR2 is a GPIF address output pin. CY7C64713 Description Page [+] Feedback ...

Page 20

... PE0 is a bidirectional I/O port pin. T0OUT is an active HIGH signal from 8051 Timer-counter0. T0OUT outputs a high level for one CLKOUT clock cycle when Timer0 overflows. If Timer0 is operated in Mode 3 (two separate timer/counters), T0OUT is active when the low byte timer/counter overflows. CY7C64713 Description Page [+] Feedback ...

Page 21

... FIFOs connected to FD[7..0] or FD[15..0]. Input N/A RDY2 is a GPIF input signal. Input N/A RDY3 is a GPIF input signal. Input N/A RDY4 is a GPIF input signal. Input N/A RDY5 is a GPIF input signal. CY7C64713 Description Page [+] Feedback ...

Page 22

... CS# is the active-LOW chip select for external memory. Output H WR# is the active-LOW write strobe output for external memory. Output H RD# is the active-LOW read strobe output for external memory. Output H OE# is the active LOW output enable for external memory. CY7C64713 Description Page [+] Feedback ...

Page 23

... Ground. Ground N/A Ground. Ground N/A Ground. Ground N/A Ground. Ground N/A Ground. N/A N/A No Connect. This pin must be left open. N/A N/A No Connect. This pin must be left open. N/A N/A No Connect. This pin must be left open. CY7C64713 Description Page [+] Feedback ...

Page 24

... LINE13 LINE12 LINE11 LINE7 LINE6 LINE5 LINE4 LINE3 COL5 COL4 COL3 COL2 COL1 LINE15 LINE14 LINE13 LINE12 LINE11 LINE7 LINE6 LINE5 LINE4 LINE3 CY7C64713 Default Access xxxxxxxx RW CLKINV CLKOE 8051RES 00000010 rrbbbbbr GSTATE IFCFG1 IFCFG0 10000000 RW FLAGA2 FLAGA1 FLAGA0 00000000 RW FLAGC2 ...

Page 25

... EDGEPF EDGEPF EDGEPF EP8 EP6 EP4 CY7C64713 Default Access COL0 0 0 11111111 R 0 PFC9 PFC8 10001000 bbbbbrbb PFC9 IN:PKTS[2] 10001000 bbbbbrbb OUT:PFC8 PFC2 PFC1 PFC0 00000000 PFC8 10001000 bbrbbrrb 0 PFC8 10001000 bbrbbrrb PFC2 PFC1 PFC0 00000000 RW 0 PFC9 PFC8 00001000 bbbbbrbb ...

Page 26

... BC6 BC5 BC4 BC3 0 BC6 BC5 BC4 BC3 BC6 BC5 BC4 BC3 BC6 BC5 BC4 BC3 CY7C64713 Default Access EP2 EP1 EP0 00xxxxxx rrbbbbbb EP0 0 IBN 00000000 RW EP0 0 IBN xxxxxx0x bbbbbbrb SUTOK SOF SUDAV 00000000 RW SUTOK SOF SUDAV 0xxxxxxx rbbbbbbb ...

Page 27

... GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 FSE LFUNC1 LFUNC0 TERMA2 TERMA1 TERMA0 CTL0E3 CTL0E2 CTL0E1/ CTL0E0/ CTL3 CTL5 CTL4 CY7C64713 Default Access BC2 BC1 BC0 xxxxxxxx RW BC10 BC9 BC8 xxxxxxxx RW BC2 BC1 BC0 xxxxxxxx RW 0 BC9 BC8 xxxxxxxx RW BC2 BC1 BC0 ...

Page 28

... RDY5 RDY4 RDY3 CY7C64713 Default Access CTL2 CTL1 CTL0 00000000 RW HOCTL2 HOCTL1 HOCTL0 00000000 RW MSTB2 MSTB1 MSTB0 00100000 RW 0 FALLING RISING 00000001 rrrrrrbb 00000010 RW TC26 TC25 TC24 00000000 RW TC18 TC17 TC16 00000000 RW TC10 TC9 TC8 00000000 RW TC2 TC1 TC0 00000001 RW 00000000 RW ...

Page 29

... EP8PF EP8EF EP8FF PS1 PT2 PS0 PT1 DONE D15 D14 D13 D12 D11 CY7C64713 Default Access xxxxxxxx 400KHZ xxxxxxxx n/a [[10 xxxxxxxx 00000111 00000000 RW A10 A9 A8 00000000 00000000 RW A10 A9 A8 00000000 SEL 00000000 IDLE 00110000 RW IT1 IE0 IT0 00000000 00000000 00000000 00000000 RW ...

Page 30

... EXF2 RCLK TCLK EXEN2 D15 D14 D13 D12 D11 RS1 RS0 1 ERESI RESI INT6 EX6 EX5 PX6 PX5 CY7C64713 Default Access xxxxxxxx xxxxxxxx R RB8_1 TI_1 RI_1 00000000 00000000 RW TR2 CT2 CPRL2 00000000 00000000 00000000 00000000 RW D10 D9 D8 00000000 00000000 01000000 00000000 RW EX4 EI² ...

Page 31

... Crystal Frequency).... 24 MHz ± 100 ppm OSC Conditions –0.05 0< V < VCC OUT I = –4 mA OUT Except D+/D– D+/D– Connected Disconnected 8051 running, connected to USB VCC min = 3.0V CY7C64713 Parallel Resonant Min Typ Max Unit 3.15 3.3 3.45 V μs 200 2 5.25 V –0.5 0 ...

Page 32

... MHz) = 3*t – t – 106 ns ACC1 CL AV DSU t (48 MHz) = 3*t – t – ns. ACC1 CL AV DSU Document #: 38-08039 Rev STBH [13 ACC1 data in Min Typ 20.83 41. follows: CY7C64713 Max Unit Notes ns 48 MHz ns 24 MHz ns 12 MHz 10 11 Page [+] Feedback ...

Page 33

... Figure 13. Data Memory Read Timing Diagram Stretch = STBL STBH t SCSL t SOEL t DSU [ ACC1 data in Stretch = 1 [14] t ACC1 Min Typ 20.83 41.66 83.2 9.6 0 Table 12 as follows: CY7C64713 DSU t DH data in Max Unit Notes ns 48 MHz ns 24 MHz ns 12 MHz 10 11 Page [+] Feedback ...

Page 34

... WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for which is based on the stretch value. Document #: 38-08039 Rev. *F Figure 14. Data Memory Write Timing Diagram t STBH data out Stretch = 1 data out Min CY7C64713 OFF1 t OFF1 Max Unit Notes 10.7 ns 11 ...

Page 35

... The timing diagram of the read and write strobing function on accessing PORTC follows. Refer to Figure 14 on page 34 for details on propagation delay of RD# and WR# signals. t STBL DATA IS UPDATED BY EXTERNAL LOGIC DATA MUST BE HELD FOR 3 CLK CYLCES t STBL CY7C64713 Figure 13 on page 33 and t STBH t STBH Page [+] Feedback ...

Page 36

... IFCLK must not exceed 48 MHz. Document #: 38-08039 Rev IFCLK t SGA t SRY t RYH valid t t SGD DAH t XCTL N N+1 t XGD Description Min 20.83 8.9 9.2 Description Min 20.83 2.9 3.7 3.2 4.5 CY7C64713 [15, 16] Max Unit 7 6.7 ns [16] Max Unit 200 11 10.7 ns Page ...

Page 37

... Clock to FLAGS Output Propagation Delay XFLG t Clock to FIFO Data Output Propagation Delay XFD Document #: 38-08039 Rev IFCLK t t RDH SRD t XFLG N OEon XFD Description Min 20.83 18.7 Description Min 20.83 12.7 3.7 CY7C64713 t OEoff [16] Max Unit 10.5 ns 10 [16] Max Unit 200 10 ...

Page 38

... SLRD to FLAGS Output Propagation Delay XFLG t SLRD to FIFO Data Output Propagation Delay XFD t SLOE Turn-on to FIFO Data Valid OEon t SLOE Turn-off to FIFO Data Hold OEoff Document #: 38-08039 Rev RDpwh t RDpwl t XFLG t XFD N N OEon OEoff Description Min CY7C64713 . Max Unit 10.5 ns 10.5 ns Page [+] Feedback ...

Page 39

... Clock to FIFO Data Hold Time FDH t Clock to FLAGS Output Propagation Time XFLG Document #: 38-08039 Rev IFCLK t WRH t SWR SFD FDH t XFLG Description Min 20.83 18.1 9.2 Description Min 20.83 12.1 3.6 3.2 4.5 CY7C64713 Z [16] Max Unit 9.5 ns [16] [16] Max Unit 200 13.5 ns Page [+] Feedback ...

Page 40

... PKTEND to Clock Setup Time SPE t Clock to PKTEND Hold Time PEH t Clock to FLAGS Output Propagation Delay XFLG Document #: 38-08039 Rev WRpwh t WRpwl t t FDH SFD t XFD Description Min t PEH t SPE t XFLG Description Min 20.83 14.6 CY7C64713 . Max Unit [16] Max Unit 9.5 ns Page [+] Feedback ...

Page 41

... Failing to adhere to this timing results in the FX2 failing to send the one byte or word short packet FDH SFD FDH FDH FDH SFD SFD X-2 X-1 X-3 CY7C64713 [16] Min Max Unit 20.83 200 ns 8.6 ns 2.5 ns 13.5 ns Figure 24 shows this scenario the value t FAH >= t ...

Page 42

... FIFOADR[1:0] to FLAGS Output Propagation Delay XFLG t FIFOADR[1:0] to FIFODATA Output Propagation Delay XFD Document #: 38-08039 Rev PEpwh t PEpwl t XFLG Description Min t OEoff t OEon Description t XFLG t XFD N N+1 Description CY7C64713 . Max Unit 115 ns Max Unit 10.5 ns 10.5 ns Max Unit 10.7 ns 14.3 ns Page [+] Feedback ...

Page 43

... In the following table, the Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz Table 28. Slave FIFO Asynchronous Address Parameters Parameter t FIFOADR[1:0] to RD/WR/PKTEND Setup Time SFA t RD/WR/PKTEND to FIFOADR[1:0] Hold Time FAH Document #: 38-08039 Rev SFA FAH [16] Description Min 20.83 t FAH t SFA Description Min CY7C64713 Max Unit 200 Unit Page [+] Feedback ...

Page 44

... IFCLK) the new data value is present the first data value read from the FIFO. To have data on the FIFO data bus, SLOE MUST also be asserted. The same sequence of events are shown for a burst read and are marked with the time indicators through 5. CY7C64713 t FAH >= t RDH ...

Page 45

... FIFO. In this example, both the data value and the PKTEND signal are clocked on the same rising edge of IFCLK. PKTEND is asserted in subsequent clock cycles. The FIFOADDR lines must be held constant during the PKTEND assertion. CY7C64713 t FAH >= t WRH T=5 ...

Page 46

... Note In burst read mode, during SLOE is assertion, the data bus driven state and outputs the previous data. After the SLRD is asserted, the data from the FIFO is driven on the data bus (SLOE must also be asserted) and then the FIFO pointer is incre- mented. CY7C64713 Table 20 on page 39 for t FAH ...

Page 47

... SLWR and the PKTEND signal at the same time. It SFD must be designed to assert the PKTEND after SLWR is deasserted and has met the minimum deasserted pulse width. The FIFOADDR lines are to be held constant during the PKTEND assertion. CY7C64713 t FAH t t WRpwl ...

Page 48

... Ordering Information Table 29. Ordering Information Ordering Code CY7C64713-128AXC 128 TQFP - Pb-free CY7C64713-100AXC 100 TQFP - Pb-free CY7C64713-56PVXC 56 SSOP - Pb-free CY7C64713-56LFXC 56 QFN - Pb-free CY7C64713-56LTXC 56 QFN CY3674 EZ-USB FX1 Development Kit Document #: 38-08039 Rev. *F Package Type RAM Size 16K 16K 16K 16K 16K CY7C64713 ...

Page 49

... Package Diagrams The FX1 is available in four packages: 56 Pin SSOP ■ 56 Pin QFN ■ 100 Pin TQFP ■ 128 Pin TQFP ■ Figure 36. 56-Pin Shrunk Small Outline Package O56 Document #: 38-08039 Rev. *F CY7C64713 51-85062-*C Page [+] Feedback ...

Page 50

... Figure 38. 56-Pin QFN (Sawn Version) Document #: 38-08039 Rev. *F Figure 37. 56-Pin QFN LF56A SIDE VIEW 0.08[0.003] C 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 6.1 0°-12° 0.30[0.012] C SEATING PLANE 0.50[0.020] CY7C64713 BOTTOM VIEW 6.1 0.18[0.007] 0.28[0.011] PIN1 ID N 0.20[0.008 0.45[0.018] SOLDERABLE EXPOSED PAD 0.24[0.009] (4X) ...

Page 51

... BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0.20 MAX. 3. DIMENSIONS IN MILLIMETERS A CY7C64713 1.40±0.05 12°±1° SEE DETAIL (8X) 0.20 MAX. ...

Page 52

... Nitrogen purge is recommended during reflow. Figure 42 on page plot of the solder mask pattern and Figure 43 on page 53 displays an X-Ray image of the assembly (darker areas indicate solder). CY7C64713 1.40±0.05 12°±1° SEE DETAIL (8X) 0.20 MAX. 1.60 MAX. ...

Page 53

... Document #: 38-08039 Rev. *F 0.017” dia Solder Mask Cu Fill Cu Fill 0.013” dia PCB Material This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane. Figure 43. X-ray Image of the Assembly CY7C64713 Page [+] Feedback ...

Page 54

... Document History Page Document Title: CY7C64713 EZ-USB FX1™ USB Microcontroller Full Speed USB Peripheral Controller Document Number: 38-08039 Orig. of REV. ECN NO. Issue Date Change ** 132091 02/10/04 KKU *A 230709 SEE ECN KKU *B 307474 SEE ECN BHA *C 392702 SEE ECN BHA *D 1664787 ...

Page 55

... Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. PSoC Solutions General psoc.cypress.com Low Power/Low Voltage clocks.cypress.com Precision Analog LCD Drive CAN 2.0b image.cypress.com USB Revised May 22, 2009 CY7C64713 psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb Page [+] Feedback ...

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