CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet
CY7C67300-100AXI
Specifications of CY7C67300-100AXI
CY7C67300-100AXI
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CY7C67300-100AXI Summary of contents
Page 1
... SIEs ■ Fast serial port supports from 9600 baud to 2.0M baud ■ SPI support in both master and slave CY7C67300 Block Diagram nRESET Control Watchdog Vbus, ID OTG D+,D- ...
Page 2
... Introduction EZ-Host™ (CY7C67300) is Cypress Semiconductor’s first full-speed, low cost multiport host/peripheral controller. EZ-Host is designed to easily interface to most high performance CPUs to add USB host functionality. EZ-Host has its own 16-bit RISC processor to act as a coprocessor or operate in standalone mode. EZ-Host also has a programmable IO interface block allowing a wide range of interface options ...
Page 3
... Port 1B OTG – OTG – OTG – OTG – OTG – OTG – Host Host Any Combination of Ports Any Combination of Ports Any Port CY7C67300 UART I2C OTG UART I2C OTG Port 2A Port 2B – – Host Host Host – – Host Peripheral – ...
Page 4
... Individually switchable internal pull up and pull down resistors on the USB data lines OTG Pins 22 Table 5. OTG Interface Pins 23 Pin Name 18 DM1A 19 DP1A 9 OTGVBUS 10 OTGID 4 CSwitchA 5 CSwitchB CY7C67300 Port 2A Port 2B Peripheral – – Peripheral Host Host Host Host Peripheral – – Peripheral – Peripheral Peripheral – ...
Page 5
... Page 1 banking is always enabled and is in effect from 0x8000 to 0x9FFF. ■ Page 2 banking is always enabled and is in effect from 0xA000 to 0xBFFF. ■ CPU memory bus strobes may wiggle when chip selects are inactive. CY7C67300 the hardware (for example, Page [+] Feedback ...
Page 6
... Note that the address lines do not map directly. 1 Figure 3. Interfacing up to 256k × 16 for External Code/Data 256k x 16 External Code/Data (Page Mode) 67 EZ-Host CY7C67300 nXMEMSEL CY7C67300 Pin Number External Memory Array 64K x 8 A[15:0] A[15:0] D[7:0] D[7:0] CE nWR WE nRD OE External Memory Array Up to 256k x 16 A[18:1] A[17:0] ...
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... Programmable delay timing for the active/inactive master SPI clock 42 ■ Auto or manual control for master mode slave select signal 43 ■ Complete access to internal memory CY7C67300 2 C interface for external serial 2 C interface for loading code out interface. The I C EEPROM ...
Page 8
... Programmable predefined frequencies ranging from 5.90 KHz to 48 MHz ■ Configurable polarity ■ Continuous and one-shot mode available Programmable Pulse/PWM Pins. Table 11. PWM Interface Pins Pin Name PWM3 PWM2 PWM1 PWM0 CY7C67300 Pin Number CTS 44 RTS 53 RXD 54 TXD 55 CTS 67 RTS 68 ...
Page 9
... EZ-Host on-chip memory directly without intervention of the CPU. The IDE interface is exposed through GPIO pins. Table 14 on page 10 achieved throughput for maximum block mode data transfer rate (with IDE_IORDY true) for the various IDE PIO modes. CY7C67300 [ ...
Page 10
... Meets OTG Supplement Requirements, see 65 Characteristics: Charge Pump on page 84 66 Charge Pump Pins 86 Table 16. Charge Pump Interface Pins 87 Pin Name 89 OTGVBUS 90 CSwitchA 91 CSwitchB CY7C67300 Actual Max Transfer Rate 3.2 MB/s 4.8 MB/s 7.38 MB/s 9.6 MB/s 12.0 MB VBUS C2 Table 134, DC for details. Pin Number 11 13 ...
Page 11
... MHz is required so the CLKSEL pin must have a 47K ohm pull up resistor to V Figure 8. Crystal Interface XTALIN CY7C67300 XTALOUT Crystal Pins Table 18. Crystal Pins Pin Name XTALIN 3.0V to 3.6V Power Supply XTALOUT CY7C67300 Pin Number 16 14 Table 83. . CC. Y1 12MHz Parallel Resonant Fundamental Mode 500uW 20-33pf ± ...
Page 12
... If OTGID is logic 1 then PORT1A (OTG) is configured as a USB peripheral ❐ If OTGID is logic 0 then PORT1A (OTG) is configured as a USB host ■ Ports 1B, 2A, and 2B default as USB peripheral ports ■ All other pins remain INPUT pins. CY7C67300 Table 19 for details. Page [+] Feedback ...
Page 13
... OTGVBUS to drop below 0.2V. Otherwise OTGVBUS only drops to V diode drops). ■ Booster circuit is turned off ■ USB transceivers is turned off ■ CPU goes into suspend mode until a programmable wakeup event CY7C67300 Reset Logic VCC 47Kohm 22pf 12MHz 22pf * Parallel Resonant Fundamental Mode 500uW 20-33pf ± ...
Page 14
... KB. However, this requires complex code banking/paging schemes via the Extended Page registers. For further information about setting up the external memory, see the External Memory Interface on page CY7C67300 shows the various memory memory map and pin names 5 ...
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... Document #: 38-08015 Rev. *J Figure 10. Memory Map ~15K External Memory USER SPACE 0x4000 - 0x7FFF Extended Page 1 0x8000 - 0x9FFF USER SPACE Banks Extended Page 2 0xA000 - 0xBFFF USER SPACE Banks USER SPACE ~8K 0xC100 - 0xDFFF BIOS CY7C67300 16K Bank Selected by 0xC018 Bank Selected by 0xC01A Page [+] Feedback ...
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... The Carry Flag bit indicates if an arithmetic operation resulted in a Carry for addition, or Borrow for subtraction. 1: Carry/Borrow occurred 0: Carry/Borrow did not occur Zero Flag (Bit 0) The Zero Flag bit indicates if an instruction execution resulted in a ‘0’. 1: Zero occurred 0: Zero did not occur CY7C67300 Address R/W 0xC000 R 0xC002 R/W 0xC004 R ...
Page 17
... The Revision field contains the silicon revision number. Document #: 38-08015 Rev Address... R/W R/W R Reserved R Hex Value 0x0100 0x000E << 0x001C 0x011C Revision... ...Revision CY7C67300 R/W R/W R Binary Value 0000 0001 0000 0000 0000 0000 0001 1100 0000 0001 0001 1100 Page [+] Feedback ...
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... MHz/6 0110 48 MHz/7 0111 48 MHz/8 1000 48 MHz/9 1001 48 MHz/10 1010 48 MHz/11 1011 48 MHz/12 1100 48 MHz/13 1101 48 MHz/14 1110 48 MHz/15 1111 48 MHz/16 Reserved Write all reserved bits with ’0’. Document #: 38-08015 Rev Reserved... - - - R CY7C67300 CPU Speed R/W R/W R Table 27. Page [+] Feedback ...
Page 19
... HPI interface read. 1: Enable wakeup on HPI interface read 0: Disable wakeup on HPI interface read GPI Wake Enable (Bit 4) The GPI Wake Enable bit enables or disables a wakeup condition to occur on a GPIO(25:24) transition. 1: Enable wakeup on GPIO(25:24) transition 0: Disable wakeup on GPIO(25:24) transition CY7C67300 Reserved HSS SPI Wake ...
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... The Host/Device 1 Interrupt Enable bit enables or disables all of the following Host/Device 1 hardware interrupts: Host 1 USB Done, Host 1 USB SOF/EOP, Host 1 Wakeup/Insert/Remove, Device 1 Reset, Device 1 SOF/EOP or WakeUp from USB, Device 1Endpoint n. 1: Enable Host 1 and Device 1 interrupt 0: Disable Host 1 and Device 1 interrupt CY7C67300 Reserved Host/Device 2 Host/Device 1 ...
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... Write all reserved bits with ’0’ Address... R/W R/W R ...Address R/W R/W R Address (Bits [15:0]) The Address field is a 16-bit field containing the breakpoint address. CY7C67300 GPIO Control Register 50). When the GPIO bit is reset, all R/W R/W R R/W R/W R Page [+] Feedback ...
Page 22
... Force Select (Bits [2:0]) The Force Select field bit selects several different test condition states on the data lines (D+/D–). Refer to Table 32. Force Select Definition Force Select [2:0] 1xx 01x 001 000 Reserved Write all reserved bits with ’0’. CY7C67300 Reserved... - - - ...
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... There are four registers dedicated to controlling the external Table 34. memory interface. Each of these registers are covered in this section and are summarized in Table 35. External Memory Control Registers Register Name Extended Page 1 Map Register Extended Page 2 Map Register Upper Address Enable Register External Memory Control Register CY7C67300 Memory Arbitration Select ...
Page 24
... Upper Address Enable (Bit 3) The Upper Address Enable bit enables/disables the four most significant bits of the external address A[18:15]. 1: Enable A[18:15] of the external memory interface for general addressing. 0: Disable A[18:15], not available. Reserved Write all reserved bits with ’0’. CY7C67300 R/W R/W R/W 0 ...
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... Write all reserved bits with ’0’. Timer Registers There are three registers dedicated to timer operations. Each of these registers are discussed in this section and are summarized in Table 39. Table 39. Timer Registers Register Name Watchdog Timer Register Timer 0 Register Timer 1 Register CY7C67300 XMEM Wait Select R/W R/W R ...
Page 26
... The Reset Strobe is a write-only bit that resets the Watchdog timer count. Set this bit to ‘1’ before the count expires to avoid a Watchdog trigger 1: Reset Count 1.4 ms Reserved 5.5 ms Write all reserved bits with ’0’. 22.0 ms 66.0 ms CY7C67300 R/W R/W R ...
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... R R Port A Force D± State R/W R/W R Port B D+ Status (Bit 15) The Port B D+ Status bit is a read only bit that indicates the value of DATA+ on Port HIGH LOW CY7C67300 R/W R/W R R/W R/W R Table 43. USB Host UART Interface on page 7, and USB ...
Page 28
... In device mode, this bit must be written as ‘0’. In host mode this bit enables or disables SOFs or EOPs for Port B. Either SOFs or EOPs are generated depending on the LOB bit in the USB n Control register when Port B is active. 1: Enable SOFs or EOPs 0: Disable SOFs or EOPs CY7C67300 Function Page [+] Feedback ...
Page 29
... R/W R Preamble Enable (Bit 7) The Preamble Enable bit enables or disables the transmission of a preamble packet before all low-speed packets. Set this bit only when communicating with a low-speed device. 1: Enable Preamble packet 0: Disable Preamble packet CY7C67300 Table 47. R/W R/W R/W R R/W R/W ...
Page 30
... Write all reserved bits with ’0’ Address... R/W R/W R ...Address R/W R/W R Address (Bits [15:0]) The Address field sets the address pointer into internal RAM or ROM Reserved - - - ...Count R/W R/W R CY7C67300 R/W R/W R R/W R/W R Count... - R/W R R/W R/W R Page [+] Feedback ...
Page 31
... Host Count specified in the Host n Count register. A Length Exception can either mean an overflow or underflow and the Overflow and Underflow flags (bits 11 and 10, respectively) must be checked to determine which event occurred overflow or underflow condition occurred 0: An overflow or underflow condition did not occur CY7C67300 Host/Device 1 Host/Device 2 Active Port Active Port A ...
Page 32
... ACK packet. 1: For non-isochronous transfers, the transaction was ACKed. For isochronous transfers, the transaction was completed successfully 0: For non-isochronous transfers, the transaction was not ACKed. For isochronous transfers, the transaction did not complete successfully Reserved - - - CY7C67300 Endpoint Select Page [+] Feedback ...
Page 33
... If an overflow condition occurs, Result [15:10] is set to ‘111111’, a 2’s complement value indicating the additional byte count of the received packet underflow condition occurs, Result [15:0] indicates the excess bytes count (number of bytes not used). Reserved Write all reserved bits with ’0’. CY7C67300 ...
Page 34
... The ID Interrupt Enable bit enables or disables the OTG ID interrupt. When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin (only supported in Port 1A). This bit is only available for Host 1 and is a reserved bit in Host 2. 1: Enable ID interrupt 0: Disable ID interrupt CY7C67300 ...
Page 35
... The ID Interrupt Flag bit indicates the status of the OTG ID interrupt (only for Port 1A). When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin. This bit is only available for Host 1 and is a reserved bit in Host 2. 1: Interrupt triggered 0: Interrupt did not trigger CY7C67300 SOF/EOP Reserved ...
Page 36
... Count... R/W R/W R ...Count R/W R/W R read, the value returned is the programmed SOF/EOP count value. Count (Bits [13:0]) The Count field sets the SOF/EOP counter duration. Reserved Write all reserved bits with ’0’. CY7C67300 R/W R/W R R/W R/W R Page [+] Feedback ...
Page 37
... X X Counter (Bits [13:0]) The Counter field contains the current value of the SOF/EOP down counter Reserved - - - ...Frame Frame (Bits [10:0]) The Frame field contains the next frame number to be trans- mitted. Reserved Write all reserved bits with ’0’. CY7C67300 Frame... ...
Page 38
... IN and OUT requests. Set this bit so that EP0 only accepts Setup packets at the start of each transfer. Clear this bit to accept IN/OUT transactions. This bit only applies to EP0. 1: Ignore IN/OUT requests 0: Do not ignore IN/OUT requests CY7C67300 Table 62. R/W R/W R/W ...
Page 39
... The Arm Enable bit arms the endpoint to transfer or receive a packet. This bit is cleared to ‘0’ when a transaction is complete. 1: Arm endpoint 0: Endpoint disarmed Reserved Write all reserved bits with ’0’ Address... R/W R/W R ...Address R/W R/W R CY7C67300 Device n Endpoint n Status Register R/W R/W R R/W R/W R Page [+] Feedback ...
Page 40
... The Address field sets the base address for the current trans- action on a signal endpoint Reserved - - - ...Count R/W R/W R Count (Bits [9:0]) The Count field sets the current transaction packet length for a single endpoint. Reserved Write all reserved bits with ’0’. CY7C67300 Count... - R/W R R/W R/W R Page [+] Feedback ...
Page 41
... Length Exception Flag (Bit 5) The Length Exception Flag bit indicates the received data in the data stage of the last transaction does not equal the maximum Endpoint Count specified in the Device n Endpoint n Count register. A Length Exception can either mean an overflow or CY7C67300 Underflow OUT ...
Page 42
... Endpoint n Count register, the Length Exception Flag bit in the Device n Endpoint n Status register is set. The value in this register is only valued when the Length Exception Flag bit is set and the Error Flag bit is not set; both bits are in the Device n Endpoint n Status register. CY7C67300 R/W ...
Page 43
... EP4 Interrupt EP3 Interrupt Enable Enable Enable R/W R/W R VBUS Interrupt Enable (Bit 15) The VBUS Interrupt Enable bit enables or disables the OTG VBUS interrupt. When enabled, this interrupt triggers on both the rising and falling edge of VBUS at the 4.4V status (only CY7C67300 ...
Page 44
... The EP1 Interrupt Enable bit enables or disables endpoint one (EP1) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device’s supplied Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception CY7C67300 Page [+] Feedback ...
Page 45
... The Address field contains the USB address of the device assigned by the host. Reserved Write all reserved bits with ’0’ Reserved - - - EP5 Interrupt EP4 Interrupt EP3 Interrupt Flag Flag Flag R/W R/W R CY7C67300 SOF/EOP Reset Interrupt Interrupt Flag Flag - R/W R/W ...
Page 46
... ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests. 1: Interrupt triggered 0: Interrupt did not trigger CY7C67300 Page [+] Feedback ...
Page 47
... Interrupt Enable register is set. Frame (Bits [10:0]) The Frame field contains the frame number from the last received SOF packet in full-speed mode. This field no function for low-speed mode SOF Timeout occurs, this field contains the last received Frame number. CY7C67300 Frame... R ...
Page 48
... Enable Discharge Enable R/W R/W R D– Reserved R VBUS Pull-up Enable (Bit 13) The VBUS Pull-up Enable bit enables or disables a 500 ohm pull up resistor onto OTG VBus. 1: 500 ohm pull up resistor enabled 0: 500 ohm pull up resistor disabled CY7C67300 Table Address R/W C098H R ...
Page 49
... GPIO Control Register 0xC006 GPIO0 Output Data Register 0xC01E GPIO0 Input Data Register 0xC020 GPIO0 Direction Register 0xC022 GPIO1 Output Data Register 0xC024 GPIO1 Input Data Register 0xC026 GPIO1 Direction Register 0xC028 CY7C67300 R/W R/W R/W R R/W R/W R R/W Page [+] Feedback ...
Page 50
... Sets IRQ1 to falling edge Interrupt 1 Enable (Bit 2) The Interrupt 1 Enable bit enables or disables IRQ1. The GPIO bit on the interrupt Enable register must also be set in order for this for this interrupt to be enabled. 1: Enable IRQ1 0: Disable IRQ1 CY7C67300 Mode Select R/W R/W ...
Page 51
... Data... 21//5 20/4 19/3 ...Data Data (Bits [15:0]) The Data field[15:0] contains the voltage values on the corre- sponding GPIO15–0 or GPIO31–16 input pins. CY7C67300 26/10 25/9 24/8 R/W R/W R 18/2 17/1 16/0 R/W R/W R 26/10 25/9 24/8 R ...
Page 52
... IDE Control Register IDE PIO Port Registers Reserved... - - - ...Reserved - - R Mode Select (Bits [2:0]) The Mode Select field sets PIO Mode IDE mode. Refer to Table 84 on page 53 CY7C67300 26/10 25/9 24/8 R/W R/W R 18/2 17/1 16/0 R/W R/W R Table 82. Address R/W 0xC048 R/W 0xC04A ...
Page 53
... MSBs of the addresses are not modified by the address counter. Therefore, the IDE Start Address and IDE Stop Address must reside within the same 16K byte block. Address (Bits [15:0]) The Address field sets the start address for an IDE block transfer. CY7C67300 R/W ...
Page 54
... Block transfer is complete 0: Clears IDE Done Flag IDE Enable (Bit 0) The IDE Enable bit starts a block transfer reset to ‘0’ when the block transfer is complete 1: Start block transfer 0: Block transfer complete Reserved Write all reserved bits with ’0’. CY7C67300 R/W R/W R ...
Page 55
... IDE PIO Port Registers [0xC050 - 0xC06F] [R/W] All IDE PIO Port registers [0xC050 - 0xC06F] in Packet Interface Extension (ATA/ATAPI-4) Specification, T13/1153D Rev 18. The table Address column denotes the CY7C67300 register address for the corresponding ATA/ATAPI register. The IDE_nCS[1:0] field defines the ATA interface CS addressing bits and the IDE_A[2:0] field define the ATA interface address bits ...
Page 56
... One Stop Bit (Bit 5) The One Stop Bit bit selects between one and two stop bits for transmit byte mode. In receive mode, the number of stop bits may vary and does not need to be fixed. 1: One stop bit 0: Two stop bits CY7C67300 CTS Receive ...
Page 57
... The Receive Ready Flag is a read only bit that indicates if the HSS receive FIFO is empty or not. 1: HSS receive FIFO is not empty (one or more bytes is reading for reading) 0: HSS receive FIFO is empty R/W R ...Baud R/W R/W R Reserved Write all reserved bits with ’0’. CY7C67300 Baud... R/W R/W R R/W R/W R Page [+] Feedback ...
Page 58
... R/W R/W R Reserved Write all reserved bits with ’0’ Reserved - - - Data R/W R/W R Data (Bits [7:0]) The Data field contains the data received transmitted on the HSS port. Reserved Write all reserved bits with ’0’. CY7C67300 R/W R/W R R/W R/W ...
Page 59
... Counter (Bits [9:0]) The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF (1023) or 2048 bytes. When the transfer is complete this register returns 0x03FF until reloaded. Reserved Write all reserved bits with ’0’. CY7C67300 R/W R/W R/W ...
Page 60
... Counter (Bits [9:0]) The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF (1023) or 2048 bytes. When the transfer is complete this register returns 0x03FF until reloaded. Reserved Write all reserved bits with ’0’. CY7C67300 R/W R/W R/W ...
Page 61
... SIE interrupt enable register. VBUS to HPI Enable (Bit 15) The VBUS to HPI Enable bit routes the OTG VBUS interrupt to the HPI port instead of the on-chip CPU. 1: Route signal to HPI port 0: Do not route signal to HPI port CY7C67300 Address R/W 0x0140 R 0x0142 ...
Page 62
... When set to ‘00’, the most significant data byte goes to HPI_D[15:8] and the least significant byte goes to HPI_D[7:0]. This is the default setting. By setting to ‘11’, the most significant data byte goes to HPI_D[7:0] and the least significant byte goes to HPI_D[15:8]. CY7C67300 Page [+] Feedback ...
Page 63
... CY7C67300 and the external host processor. If enabled, the HPI Mailbox RX Full interrupt triggers when the external host processor writes to this register. When the CY7C67300 reads this register the HPI Mailbox RX Full interrupt is automatically cleared. If enabled, the HPI Mailbox TX Empty interrupt triggers when the external host processor reads from this register ...
Page 64
... CY7C67300 CPU wrote to the SIE2msg register. This bit is cleared on an HPI read. 1: The SIE2msg register was written by the CY7C67300 CPU 0: The SIE2msg register was not written by the CY7C67300 CPU SIE1msg (Bit 4) The SIE1msg Flag bit is a read only bit that indicates if the CY7C67300 CPU wrote to the SIE1msg register ...
Page 65
... HPI Mailbox register. 1: Interrupt triggered 0: Interrupt did not trigger Address 0xC0C8 R/W 0xC0CA R/W 0xC0CC R/W 0xC0CE R 0xC0D0 W 0xC0D2 R/W 0xC0D4 R/W 0xC0D6 R/W 0xC0D8 R/W 0xC0DA R/W 0xC0DC R/W 0xC0DE R/W CY7C67300 Table 104. R/W Page [+] Feedback ...
Page 66
... MHz count in half bit times of auto transfer delay for: SS low to SCK 1 MHz active, SCK inactive to SS high, SS high time. This field only applies to master mode. 750 KHz CY7C67300 Reserved R/W R/W ...
Page 67
... The Transmit Bit Length field controls whether a full byte or partial byte transmitted. If Transmit Bit Length is ‘000’ then a full byte is transmitted. If Transmit Bit Length is ‘001’ to ‘111’, then the value indicates the number of bits that are be transmitted. CY7C67300 Read Transmit ...
Page 68
... SPI Control register is set to ‘1’, then a Tx FIFO underflow occurred. Similarly, when set with the Receive Full bit of the SPI Control register FIFO overflow occured.This bit automatically clears when the SPI FIFO Init Enable bit of the SPI Control register is set. 1: Indicates FIFO error 0: Indicates no FIFO error CY7C67300 ...
Page 69
... Reserved Write all reserved bits with ’0’ CRC CRC Receive Enable Clear CRC R/W R/W R ...Reserved - - - CRC Mode (Bits [15:14) The CRCMode field selects the CRC polynomial as defined in Table 112 on page CY7C67300 Transmit Transfer Interrupt Interrupt Clear Clear - One in Zero in Reserved ...
Page 70
... CRC... R/W R/W R ...CRC R/W R/W R CRC (Bits [15:0]) The CRC field contains the SPI CRC. In CRC Mode CRC7, the CRC value is a seven bit value [6:0]. Therefore, bits [15:7] are invalid in CRC7 mode. CY7C67300 R/W R/W R R/W R/W R Page [+] Feedback ...
Page 71
... The Data field contains data received transmitted on the SPI port. Reserved Write all reserved bits with ’0’ Address... R/W R/W R ...Address R/W R/W R Address (Bits [15:0]) The Address field sets the base address for the SPI transmit DMA. CY7C67300 R/W R/W R R/W R/W R ...
Page 72
... Write all reserved bits with ’0’ Address... R/W R/W R ...Address R/W R/W R Address (Bits [15:0]) The Address field sets the base address for the SPI receive DMA Reserved - - - ...Count R/W R/W R CY7C67300 Count... R/W R/W R R/W R/W R R/W R/W R R/W R/W R Count... R/W R/W ...
Page 73
... KBaud UART Enable (Bit 0) The UART Enable bit enables or disables the UART. 1: Enable UART 0: Disable UART. This allows GPIO28 and GPIO27 to be used for general use. Reserved Write all reserved bits with ’0’. CY7C67300 Address R/W 0xC0E0 R/W 0xC0E2 R 0xC0E4 ...
Page 74
... Transmit buffer full (transmit busy) 0: Transmit buffer is empty and ready for a new byte of data Reserved - - - Data R/W R/W R Data (Bits [7:0]) The Data field is where the UART data to be transmitted or received is located. Reserved Write all reserved bits with ’0’. CY7C67300 Receive Full Transmit Full - ...
Page 75
... Polarity Polarity Enable Select Select R/W R/W R Table 126. Prescaler Select Definition Prescale Select [11:9] 000 001 010 011 100 101 110 111 CY7C67300 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Prescale Mode Select Select R/W R/W ...
Page 76
... The PWM 0 Enable bit enables or disables PWM 0. 1: Enable PWM 0 0: Disable PWM Reserved - - - ...Count R/W R/W R Count (Bits [9:0]) The Count field sets the maximum cycle time. Reserved Write all reserved bits with ’0’. CY7C67300 Count... - R/W R R/W R/W R Page [+] Feedback ...
Page 77
... Write all reserved bits with ’0’ Reserved - - - ...Address R/W R/W R stays at ‘0’. If the PWM Stop value is greater then the PWM Maximum Count value then the output stays at true. Reserved Write all reserved bits with ’0’. CY7C67300 Address... - R/W R R/W R/W R Address... - ...
Page 78
... R/W R ...Count R/W R/W R Count (Bits [9:0]) The Count field designates the number of cycles (plus one) to run when in one shot mode. For example, Cycles = PWM Cycle Count + 1, therefore for two cycles set PWM Cycle Count = 1. CY7C67300 R/W R/W R R/W R/W R Page ...
Page 79
... CTS: HSS CTS IO D14: External Memory Data Bus RTS: HSS RTS IO D13: External Memory Data Bus RXD: HSS RXD (Data is received on this pin) IO D12: External Memory Data Bus TXD: HSS TXD (Data is transmitted from this pin) CY7C67300 75 GND 74 D8/MISO 73 D9/nSSI 72 D10/SCK 71 ...
Page 80
... MHz is required for normal operation so the CLKSEL pin must have a 47K ohm pull After reset this pin functions as A15. IO GPIO31: General Purpose IO SCK: I2C EEPROM SCK IO GPIO30: General Purpose IO SDA: I2C EEPROM SDA CY7C67300 CC. Page [+] Feedback ...
Page 81
... GPIO15: General Purpose IO D15: D15 for HPI or IDE nSSI: SPI nSSI IO GPIO14: General Purpose IO D14: D14 for HPI or IDE IO GPIO13: General Purpose IO D13: D13 for HPI or IDE IO GPIO12: General Purpose IO D12: D12 for HPI or IDE CY7C67300 = 3.0V, a 10K to CC Page [+] Feedback ...
Page 82
... Booster Power input : 2.7V to 3.6V Analog Booster switching output Output Ground Booster Ground Analog IO USB OTG Vbus Analog Charge Pump Capacitor Analog Charge Pump Capacitor Power USB Power Ground USB Ground Power Main V CC Ground Main Ground CY7C67300 Description Page [+] Feedback ...
Page 83
... Parallel Resonant Min Typical –500 20 Conditions 0< V < OUT I = –4 mA OUT Except D+/D– D+/D– 4 transceivers powered 4 transceivers powered to provide a nominal 3.3V V supply CY7C67300 , AV ) ...........................+3.0V to +3. [7] ) .........................+2.7V to +3.6V CC Max Unit 12 MHz +500 PPM 33 pF 500 µ Min Typ. Max 3 ...
Page 84
... LOAD LOAD LOAD 0V< V < 5.25V BUS mA 3.3V LOAD not being driven BUS Pull up voltage = 3.0V values when only two transceivers are powered. CY7C67300 Min Typ. Max Unit μ A 210 500 μ μ A 190 500 μ Min Typ. Max Unit 4 ...
Page 85
... Clock is 12 MHz nominal. v 12. XINH is required obtain an internal 50/50 duty cycle clock. Document #: 38-08015 Rev RESET t IOACT Reset Timing Min 16 200 t LOW t FALL Clock Timing Min 1.5 83. CY7C67300 Typical Max Unit [11] clocks µs t RISE Typical Max Unit 12.0 MHz 3.0 3.6 V 83.33 83 ...
Page 86
... External SRAM access time = 12 ns for zero and one wait states. The External SRAM access time = – 1)*T for wait states = n, n > MHz AC clock period. 15. Read timing is applicable for nXMEMSEL, nXRAMSEL, and nXROMSEL. Document #: 38-08015 Rev RPW t AC Data Valid Min CY7C67300 t CDH t RDH Typical Max Unit Page ...
Page 87
... The write pulse width = 18.8 ns min. for zero and one wait states. The write pulse = 18 – 1)*T for wait states = n, n > MHz clock period. WPW 17. Write timing is applicable for nXMEMSEL, nXRAMSEL and nXROMSEL. Document #: 38-08015 Rev CSW t WPW t DW Data Valid Min 4.5 13 CY7C67300 Typical Max Unit Page [+] Feedback ...
Page 88
... Input Fall Time F t Stop Setup Time SU.STO t Data Out Hold Time DH Document #: 38-08015 Rev LOW HIGH SU.DAT t HD.DAT t DH Min Typical 1300 600 900 1300 600 600 0 100 600 0 CY7C67300 BUF t SU.STO Max Unit 400 kHz 300 ns 300 Page [+] Feedback ...
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... Data Setup DSU t Write Data Hold WDH t Write Pulse Width WP t Write Cycle Time CYC Notes 18 system clock period = 1/48 MHz. Document #: 38-08015 Rev CYC CSH t t DSU WDH Min Typical Max –1 –1 –1 – CY7C67300 Unit [18] T [18] T Page [+] Feedback ...
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... Read Data Hold, relative to the earlier of RDH HPI_nRD rising or HPI_nCS rising t Read Pulse Width RP t Read Cycle Time CYC Document #: 38-08015 Rev CYC CSH t RDH t t ACC RDH Min Typical –1 –1 –1 –1 1 CY7C67300 Max Unit [18 [18] T [18] T Page [+] Feedback ...
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... BT t GAP = (HSS_GAP – 9) BT, where BT is the bit time, and HSS_GAP is the content of the HSS bit 1 bit 2 bit 3 bit 4 bit +/- 5% CY7C67300 CPU may start another BYTE transmit right after TxRdy goes high bit 3 bit 4 bit 5 bit 6 bit 7 stop bit start bit ...
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... Host/Device Host/Device Host/Device OTG 2A Wake 1B Wake 1A Wake Wake Enable Enable Enable Enable Reserved GPI Reserved Wake Enable CY7C67300 tCTShold tCTSsetup Bit 10 Bit 9 Bit 8 Default High Bit 2 Bit 1 Bit 0 Default Low 0000 0000 0000 0000 SOF/EOP1 to Reset2 to HPI HPI Swap 1 0001 0100 ...
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... XOFF XOFF Polarity Polarity Enable Select Select Receive Done One Transmit Packet Mode Interrupt Flag Stop Bit Ready Select HSS Baud... CY7C67300 Bit 10 Bit 9 Bit 8 Default High Bit 2 Bit 1 Bit 0 Default Low 0000 0000 Lock WDT Reset 0000 0000 Enable Enable ...
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... Interrupt Count Counter... Count... Port A Port B Connect Port A Con- Reserved Wake Interrupt Change nect Change Enable Interrupt Interrupt Enable Enable CY7C67300 Bit 10 Bit 9 Bit 8 Default High Bit 2 Bit 1 Bit 0 Default Low Counter... 0000 0000 0000 0000 0000 0000 Arm 0000 0000 ...
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... Enable Clear CRC Scale Select Baud Select Reserved Prescale Select PWM2 PWM1 PWM0 PWM3 Polarity Select Polarity Select Polarity Select Enable CY7C67300 Bit 10 Bit 9 Bit 8 Default High Bit 2 Bit 1 Bit 0 Default Low Wake SOF/EOP Reset 0000 0000 Interrupt Interrupt Interrupt Enable ...
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... Document #: 38-08015 Rev. *J Bit 14 Bit 13 Bit 12 Bit 11 Bit 6 Bit 5 Bit 4 Bit 3 ID Reserved SOF/EOP2 Reserved Flag Flag SIE1msg Done2 Flag CY7C67300 Bit 10 Bit 9 Bit 8 Default High Bit 2 Bit 1 Bit 0 Default Low Address... 0000 0000 0000 0000 0000 0000 0000 0000 SOF/EOP1 Reset2 Mailbox In ...
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... Ordering Information Table 143. Ordering Information Ordering Code CY7C67300-100AXI 100 TQFP CY7C67300-100AXA 100 TQFP CY7C67300-100AXIT 100 TQFP, tape and reel CY7C67300-100AXAT 100 TQFP, tape and reel CY3663 Development Kit Package Diagrams Figure 12. 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100SA 16.00±0.25 SQ 14.00± ...
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... Document History Page Document Title: CY7C67300 EZ-Host™ Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Document Number: 38-08015 Orig. of REV. ECN NO. Change sion Date ** 111872 MUL *A 116989 MUL *B 125262 MUL *C 126210 MUL *D 127335 KKV *E 129395 MUL ...
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... I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders. PSoC Solutions psoc.cypress.com General clocks.cypress.com Low Power/Low Voltage Precision Analog LCD Drive image.cypress.com CAN 2.0b USB Revised July 28, 2008 CY7C67300 psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb Page [+] Feedback ...