CY7C63413-PVC Cypress Semiconductor Corp, CY7C63413-PVC Datasheet
CY7C63413-PVC
Specifications of CY7C63413-PVC
Available stocks
Related parts for CY7C63413-PVC
CY7C63413-PVC Summary of contents
Page 1
... CY7C63411/12/13 CY7C63511/12/13 Low-Speed, High I/O, 1.5 Mbps USB Controller Cypress Semiconductor Corporation • 3901 North First Street • San Jose fax id: 3404 CY7C63411/12/13 CY7C63511/12/13 • CA 95134 • 408-943-2600 February 1997 Revised January 7, 1998 ...
Page 2
FEATURES ..................................................................................................................................... 5 2.0 FUNCTIONAL OVERVIEW ............................................................................................................. 6 3.0 PIN ASSIGNMENTS ....................................................................................................................... 8 4.0 PROGRAMMING MODEL ............................................................................................................... 8 4.1 14-bit Program Counter (PC) ........................................................................................................... 8 4.2 8-bit Accumulator (A) ....................................................................................................................... 8 4.3 8-bit Index Register (X) .................................................................................................................... 8 4.4 ...
Page 3
INTERRUPTS .............................................................................................................................. 22 15.1 Interrupt Vectors .......................................................................................................................... 23 15.2 Interrupt Latency .......................................................................................................................... 23 15.2.1 USB Bus Reset Interrupt .................................................................................................................... 23 15.2.2 Timer Interrupt .................................................................................................................................... 24 15.2.3 USB Endpoint Interrupts ..................................................................................................................... 24 15.2.4 DAC Interrupt ...................................................................................................................................... 24 15.2.5 GPIO Interrupt ...
Page 4
Figure 6-1. Program Memory Space with Interrupt Vector Table ......................................................... 11 Figure 7-1. Clock Oscillator On-chip Circuit .......................................................................................... 14 Figure 8-1. Watch Dog Reset (WDR) ................................................................................................... 15 Figure 9-1. Block Diagram of a GPIO Line ........................................................................................... 15 Figure 9-2. Port ...
Page 5
... RAM — 4 Kbytes of EPROM (CY7C63411, CY7C63511) — 6 Kbytes of EPROM (CY7C63412, CY7C63512) — 8 Kbytes of EPROM (CY7C63413, CY7C63513) • Interface can auto-configure to operate as PS2 or USB • I/O port — 24 General Purpose I/O (GPIO) pins (Port capable of sinking 7 mA per pin (typical) — ...
Page 6
... The CY7C63411/12/13 and CY7C63511/12/13 are offered with three EPROM options to maximize flexibility and minimize cost. The CY7C63411 and CY7C63511 have 4 Kilobytes of EPROM. The CY7C63412 and CY7C63512 have 6 Kilobytes of EPROM. The CY7C63413 and CY7C63513 have 8 Kilobytes of EPROM. These parts include power-on reset logic, a watchdog timer, a vectored interrupt controller, and a 12-bit free-running timer. The power-on reset (POR) logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at EPROM address 0x0000h ...
Page 7
Logic Block Diagram 6 MHz ceramic resonator OSC 12 MHz 6 MHz 12 MHz USB 8-bit Transceiver CPU USB EPROM SIE 4/6/8 Kbyte RAM Interrupt 256 byte Controller 12-bit GPIO Timer PORT 0 GPIO PORT 1 GPIO PORT 2 ...
Page 8
Pin Assignments CY7C63411/12/13 Name I/O 40-Pin 48-Pin D+, D– I/O 1,2 P0[7:0] 15,26,16,25, 17,32,18,31, I/O 17,24,18,23 19,30,20,29 P1[7:0] 11,30,12,29, 11,38,12,37, I/O 13,28,14,27 13,36,14,35 P2[7:0] 7,34,8,33, 7,42,8,41, I/O 9,32,10,31 9,40,10,39 P3[7:0] 3,38,4,37, 3,46,4,45, I/O 5,36,6,35 5,44,6,43 DAC[7:0] I/O n/a XTAL ...
Page 9
During an interrupt acknowledge, interrupts are disabled and the 14-bit program counter, carry flag, and zero flag are written as two bytes of data memory. The first byte is stored in the memory addressed by the program stack pointer, then ...
Page 10
Instruction Set Summary MNEMONIC operand HALT ADD A,expr data ADD A,[expr] direct ADD A,[X+expr] index ADC A,expr data ADC A,[expr] direct ADC A,[X+expr] index SUB A,expr data SUB A,[expr] direct SUB A,[X+expr] index SBB A,expr data SBB A,[expr] direct ...
Page 11
... Reserved 0x0012 Reserved 0x0014 DAC interrupt vector 0x0016 GPIO interrupt vector 0x0018 Reserved 0x001A Program Memory begins here 0x0FFF 4 KB PROM ends here (CY7C63411,CY7C63511) 0x17FF 6 KB PROM ends here (CY7C63412, CY7C63512) ( bytes) 0x1FDF 8 KB PROM ends here (CY7C63413, CY7C63513) 11 CY7C63411/12/13 CY7C63511/12/13 ...
Page 12
Data Memory Organization The CY7C63411/12/13 and CY7C63511/12/13 microcontrollers provide 256 bytes of data RAM. In normal usage, the SRAM is partitioned into four areas: program stack, data stack, user variables and USB endpoint FIFOs as shown below: after reset ...
Page 13
I/O Register Summary I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads the selected port into the accumulator. IOWR writes data from the accumulator to the selected port. Indexed I/O Write ...
Page 14
Clocking Clock Distribution clk1x (to USB SIE) clk2x (to Microcontroller) The XTAL and XTAL are the clock pins to the microcontroller. The user can connect a low-cost ceramic resonator OUT external oscillator can be connected to ...
Page 15
Watch Dog Reset (WDR) The Watch Dog Timer Reset (WDR) occurs when the Most Significant Bit (MSB) of the 2-bit Watch Dog Timer Register transitions from LOW to HIGH. In addition to the normal reset initialization noted under “Reset,” ...
Page 16
GPIO port is configured for CMOS outputs and the output data bit is written as a “1”. Q2 and Q3 are sized to sink and source, respectively, roughly the same amount of current to ...
Page 17
Port Configuration bits “Resistive” mode Kohm pull-up resistor is conditionally enabled for all pins of a GPIO port. The resistor is enabled for any pin that has been written as a “1.” ...
Page 18
The DAC port provides the CY7C63511/12/13 with 8 programmable current sink I/O pins. Writing a “1” DAC I/O pin disables the output current sink (Isink DAC) and drives the I/O pin HIGH through an integrated 14 Kohm resistor. ...
Page 19
Fill and empty the FIFOs • Suspend/Resume coordination • Verify and select Data toggle values 11.1 USB Enumeration The enumeration sequence is shown below: 1. The host computer sends a Setup packet followed by a Data packet to USB ...
Page 20
Control Bits Control action 000 Not forcing (SIE controls driver) 001 Force K (D+ high, D– low) 010 Force J (D+ low, D– high) 011 Force SE0 (D+ low, D– low) 100 Force SE0 (D low, D+ low) 101 Force ...
Page 21
The ‘set-up’ PID status (bit[7]) is forced high from the start of the data packet phase of the set-up transaction, until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during ...
Page 22
Processor Status and Control Register R/W IRQ Watch Dog USB Bus pending Reset Reset Figure 14-1. Processor Status and Control Register 0xFFh The “run” (bit 0) is manipulated by the HALT instruction. When Halt is executed, ...
Page 23
Reserved Reserved Reserved Figure 15-2. USB End Point Interrupt Enable Register 0x21h (read/write) Pending interrupt requests are recognized during the last clock cycle of the current instruction. When servicing an interrupt, the hardware will first disable all interrupts ...
Page 24
Timer Interrupt There are two timer interrupts: the 128 s interrupt and the 1.024 ms interrupt. The user should disable both timer interrupts before going into the suspend mode to avoid possible conflicts between servicing the interrupts first or ...
Page 25
The ‘In’ column represents the SIE’s response to the token type. A disabled endpoint will remain such until firmware changes it, and all endpoints reset to disabled. Any Setup packet to an enabled and accepting endpoint will be changed by ...
Page 26
Table 16-3. Details of Modes for Differing Traffic Conditions End Point Mode token count buffer Setup Packet (if accepting) SeeTable 16-1. Setup <= 10 data SeeTable 16-1. Setup > 10 junk See Table 16-1. Setup x ...
Page 27
Table 16-3. Details of Modes for Differing Traffic Conditions (continued Out Out != Out > Out ...
Page 28
DC Characteristics Fosc = 6 MHz; Operating Temperature = 0 to 70°C Parameter General V Operating Voltage CC (1) V Operating Voltage CC ( Operating Supply Current CC1 cc I Vcc = 4.35 V CC2 I Supply ...
Page 29
Switching Characteristics Parameter Description Clock t Input clock cycle time CYC t Clock HIGH time CH t Clock LOW time CL USB Driver Characteristics t Transition Rise Time (notes 2,3, Transition Rise Time (notes 2,3, ...
Page 30
crs 10 Figure 19-2. USB Data Signal Timing T PERIOD Differential Data Lines Figure 19-3. Receiver Jitter Tolerance T PERIOD Crossover Point Differential Data Lines Diff. Data ...
Page 31
... T PERIOD Differential Data Lines 20.0 Ordering Information EPROM Ordering Code Size CY7C63411- CY7C63411-PVC 4 KB CY7C63412- CY7C63412-PVC 6 KB CY7C63413- CY7C63413-PVC 8 KB CY7C63413- CY7C63413-WVC 8 KB CY7C63511-PVC 4 KB CY7C63512-PVC 6 KB CY7C63513-PVC 8 KB CY7C63513-WVC 8 KB Document #: 38-00589-D Crossover Points Consecutive Transitions PERIOD xJR1 Paired Transitions ...
Page 32
Package Diagrams 48-Lead Shrunk Small Outline Package O48 40-Lead (600-Mil) Molded DIP P17 32 CY7C63411/12/13 CY7C63511/12/13 ...
Page 33
... Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...