CY7C68016A-56LTXC Cypress Semiconductor Corp, CY7C68016A-56LTXC Datasheet

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CY7C68016A-56LTXC

Manufacturer Part Number
CY7C68016A-56LTXC
Description
IC MCU USB PHERIPH FX2LP 56VQFN
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB FX2LP™r
Type
USB Peripheral Controllerr
Datasheet

Specifications of CY7C68016A-56LTXC

Package / Case
56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
Applications
USB Microcontroller
Core Processor
8051
Program Memory Type
ROMless
Controller Series
CY7C680xx
Ram Size
16K x 8
Interface
I²C, USB, USART
Number Of I /o
26
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Mounting Style
SMD/SMT
Operating Temperature Range
0 C to + 70 C
Supply Current
50 mA
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4611B - KIT USB TO ATA REFERENCE DESIGN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-2936
1. Features (CY7C68013A/14A/15A/16A)
Cypress Semiconductor Corporation
Document #: 38-08032 Rev. *M
USB 2.0 USB IF High Speed Certified (TID # 40460272)
Single Chip Integrated USB 2.0 Transceiver, Smart SIE, and
Enhanced 8051 Microprocessor
Fit, Form, and Function Compatible with the FX2
Ultra Low Power: I
Software: 8051 Code Runs from:
16 KBytes of On-Chip Code/Data RAM
Four Programmable BULK/INTERRUPT/ISOCHRONOUS
Endpoints
Additional Programmable (BULK/INTERRUPT) 64 Byte
Endpoint
8-bit or 16-bit External Data Interface
Smart Media Standard ECC Generation
Pin compatible
Object-code-compatible
Functionally Compatible (FX2LP is a superset)
Ideal for bus and battery powered applications
Internal RAM, which is downloaded through USB
Internal RAM, which is loaded from EEPROM
External memory device (128 pin package)
Buffering options: double, triple, and quad
CC
No More than 85 mA in any Mode
198 Champion Court
EZ-USB FX2LP™ USB Microcontroller
High Speed USB Peripheral Controller
GPIF (General Programmable Interface)
Integrated, Industry Standard Enhanced 8051
3.3V Operation with 5V Tolerant Inputs
Vectored USB Interrupts and GPIF/FIFO Interrupts
Separate Data Buffers for the Setup and Data Portions of a
CONTROL Transfer
Integrated I
Four Integrated FIFOs
Available in Commercial and Industrial Temperature Grade
(all packages except VFBGA)
Enables direct connection to most parallel interfaces
Programmable waveform descriptors and configuration
registers to define waveforms
Supports multiple Ready (RDY) inputs and Control (CTL)
outputs
48 MHz, 24 MHz, or 12 MHz CPU operation
Four clocks per instruction cycle
Two USARTS
Three counter/timers
Expanded interrupt system
Two data pointers
Integrated glue logic and FIFOs lower system cost
Automatic conversion to and from 16-bit buses
Master or slave operation
Uses external clock or asynchronous strobes
Easy interface to ASIC and DSP ICs
San Jose
2
C Controller, Runs at 100 or 400 kHz
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
,
CA 95134-1709
Revised May 22, 2009
• 408-943-2600
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Related parts for CY7C68016A-56LTXC

CY7C68016A-56LTXC Summary of contents

Page 1

... Uses external clock or asynchronous strobes ❐ Easy interface to ASIC and DSP ICs ❐ Available in Commercial and Industrial Temperature Grade ■ (all packages except VFBGA) • 198 Champion Court • San Jose CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A , CA 95134-1709 • 408-943-2600 Revised May 22, 2009 [+] Feedback ...

Page 2

... TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs), 56-pin ❐ QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin VF- BGA (24 GPIOs) 1.2 Features (CY7C68015A/16A only) CY7C68016A: Ideal for Battery Powered Applications ■ Suspend current: 100 μA (typ) ❐ CY7C68015A: Ideal for Non-battery Powered Applications ■ ...

Page 3

... These signals must be pulled up to 3.3V, even device is connected. 3.4 Buses All packages, 8-bit or 16-bit “FIFO” bidirectional data bus, multi- plexed on I/O ports B and D. 128-pin package: adds 16-bit output-only 8051 address bus, 8-bit bidirectional data bus. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 24 MHz × PLL [1] on page 4 ...

Page 4

... USB interrupt source, the FX2LP provides a second level of interrupt vectoring, called Autovectoring. When a USB interrupt is asserted, the FX2LP pushes the program counter to its stack, and then jumps to the address 0x0043 where it expects to find a “jump” instruction to the USB Interrupt service routine. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A SCON1 ...

Page 5

... Bus errors exceeded the programmed limit reserved reserved ISO EP2 OUT PID sequence error ISO EP4 OUT PID sequence error ISO EP6 OUT PID sequence error ISO EP8 OUT PID sequence error CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Notes Table 4 on page 6 shows the priority Page [+] Feedback ...

Page 6

... A powered reset is when the FX2LP powered on and operating and the RESET# pin is asserted. Cypress provides an application note which describes and recommends power on reset implementation. For more infor- mation about reset implementation for the FX2 family of products visit http://www.cypress.com. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Notes [3] Page [+] Feedback ...

Page 7

... Setup data pointer ■ interface boot load. ■ 3.10.3 External Code Memory The bottom 16 KBytes of program memory is external and therefore the bottom 16 KBytes of internal RAM is accessible only as a data memory. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A RESET Powered Reset Page [+] Feedback ...

Page 8

... External 40 KBytes Code External Memory Data (PSEN#) Memory (RD#,WR#) (Ok to populate (OK to populate data memory program here—RD#/WR# memory here— strobes are not PSEN# strobe active) is not active) Data Code 2 C interface boot access CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Page [+] Feedback ...

Page 9

... Bytes EP0 IN/OUT E740 E73F 64 Bytes RESERVED E700 E6FF 8051 Addressable Registers (512) E500 E4FF Reserved (128) E480 E47F 128 bytes GPIF Waveforms E400 E3FF Reserved (512) E200 E1FF 512 bytes 8051 xdata RAM E000 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Page [+] Feedback ...

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... EP6 EP6 EP6 EP6 EP6 512 512 512 1024 1024 512 512 512 EP8 EP8 512 512 512 1024 1024 512 512 512 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A EP2 EP2 EP2 EP2 EP2 512 1024 1024 1024 512 1024 512 EP6 1024 ...

Page 11

... FIFO. The slave interface can also operate asynchronously, where the SLRD and SLWR signals act directly as strobes, rather than a clock qualifier as in synchronous mode. The signals SLRD, SLWR, SLOE and PKTEND are gated by the signal SLCS#. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A int 64 int 64 iso out (2× ...

Page 12

... After the data has been downloaded from the host, a “loader” can execute from internal RAM to transfer downloaded data to external memory. Document #: 38-08032 Rev. *M CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 3.15 ECC Generation The EZ-USB can calculate ECCs (Error Correcting Codes) on data that passes across its GPIF or Slave FIFO interfaces. There are two ECC configurations: Two ECCs, each calculated over 256 bytes (SmartMedia Standard) ...

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... CY7C68013A-100AXC or CY7C68014A-100AXC CY7C68013-128AC CY7C68013A-128AXC or CY7C68014A-128AXC Note 9. This EEPROM does not have address pins. Document #: 38-08032 Rev. *M CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 2 3.18 Interface Boot Load Access At power on reset the I VID/PID/DID configuration bytes and KBytes of program/data. The available RAM spaces are 16 KBytes from 2 0x0000– ...

Page 14

... CY7C68015A and CY7C68016A are available in 56-pin QFN package only. Two additional GPIO signals are available on the CY7C68015A and CY7C68016A to provide more flexibility when neither IFCLK or CLKOUT are needed in the 56-pin package. USB developers wanting to convert their FX2 56-pin application to a bus-powered system directly benefit from these additional signals ...

Page 15

... PORTC2/GPIFADR2 PORTC1/GPIFADR1 PORTC0/GPIFADR0 PE7/GPIFADR8 PE6/T2EX PE5/INT6 PE4/RxD1OUT PE3/RxD0OUT PE2/T2OUT PE1/T1OUT PE0/T0OUT Document #: 38-08032 Rev. *M CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 6. Signal Port GPIF Master PD7 FD[15] PD6 FD[14] PD5 FD[13] PD4 FD[12] PD3 FD[11] PD2 FD[10] PD1 FD[9] PD0 FD[8] FD[7] PB7 ...

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... A14 24 A15 25 VCC 26 GND 27 INT4 *IFCLK 32 RESERVED 33 BKPT SCL 36 SDA 37 OE# 38 Document #: 38-08032 Rev. *M CY7C68013A/CY7C68014A 128-pin TQFP * denotes polarity programmable CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 102 PD0/FD8 101 *WAKEUP 100 VCC 99 RESET# 98 CTL5 GND 92 PA7/*FLAGD/SLCS# 91 PA6/*PKTEND 90 PA5/FIFOADR1 89 PA4/FIFOADR0 PA3/*WU2 ...

Page 17

... VCC 20 GND 21 INT4 *IFCLK 26 RESERVED 27 BKPT 28 SCL 29 SDA 30 Document #: 38-08032 Rev. *M PA7/*FLAGD/SLCS# CY7C68013A/CY7C68014A 100-pin TQFP * denotes programmable polarity CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A PD0/FD8 80 *WAKEUP 79 VCC 78 RESET# 77 CTL5 76 GND 75 74 PA6/*PKTEND 73 PA5/FIFOADR1 72 PA4/FIFOADR0 71 PA3/*WU2 70 PA2/*SLOE 69 PA1/INT1# 68 PA0/INT0# 67 VCC ...

Page 18

... DPLUS PA2/*SLOE DMINUS PA1/INT1# AGND PA0/INT0# VCC VCC GND CTL2/*FLAGC *IFCLK CTL1/*FLAGB RESERVED CTL0/*FLAGA SCL GND SDA VCC VCC GND PB0/FD0 PB7/FD7 PB1/FD1 PB6/FD6 PB2/FD2 PB5/FD5 PB3/FD3 PB4/FD4 * denotes programmable polarity CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Page [+] Feedback ...

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... AVCC 7 DPLUS 8 DMINUS 9 AGND 10 VCC 11 GND 12 *IFCLK/**PE0 13 RESERVED 14 Document #: 38-08032 Rev. *M CY7C68013A/CY7C68014A & CY7C68015A/CY7C68016A 56-pin QFN * denotes programmable polarity ** denotes CY7C68015A/CY7C68016A pinout CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A RESET# 42 GND 41 PA7/*FLAGD/SLCS# 40 PA6/*PKTEND 39 PA5/FIFOADR1 38 PA4/FIFOADR0 37 PA3/*WU2 36 PA2/*SLOE 35 PA1/INT1# 34 PA0/INT0# ...

Page 20

... Figure 11. CY7C68013A 56-pin VFBGA Pin Assignment - Top View Document #: 38-08032 Rev CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Page [+] Feedback ...

Page 21

... I/O/Z Z Output H Program Store Enable. This active-LOW signal indicates an 8051 code fetch from external memory active for program memory fetches from 0x4000–0xFFFF when the EA pin is LOW, or from 0x0000–0xFFFF when the EA pin is HIGH. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page [+] Feedback ...

Page 22

... I/O/Z I Multiplexed pin whose function is selected by two bits: (PA2) IFCONFIG[1:0]. PA2 is a bidirectional I/O port pin. SLOE is an input-only output enable with program- mable polarity (FIFOPINPOLAR.4) for the slave FIFOs connected to FD[7..0] or FD[15..0]. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page [+] Feedback ...

Page 23

... PB3 is a bidirectional I/O port pin. FD[3] is the bidirectional FIFO/GPIF data bus. I/O/Z I Multiplexed pin whose function is selected by the (PB4) following bits: IFCONFIG[1..0]. PB4 is a bidirectional I/O port pin. FD[4] is the bidirectional FIFO/GPIF data bus. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page [+] Feedback ...

Page 24

... Multiplexed pin whose function is selected by the (PD0) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[8] is the bidirectional FIFO/GPIF data bus. I/O/Z I Multiplexed pin whose function is selected by the (PD1) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[9] is the bidirectional FIFO/GPIF data bus. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page [+] Feedback ...

Page 25

... PORTECFG.3 bit. PE3 is a bidirectional I/O port pin. RXD0OUT is an active-HIGH signal from 8051 UART0. If RXD0OUT is selected and UART0 is in Mode 0, this pin provides the output data for UART0 only when sync mode. Otherwise CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page [+] Feedback ...

Page 26

... RDY5 is a GPIF input signal. O/Z H Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. CTL0 is a GPIF control output. FLAGA is a programmable slave-FIFO output status flag signal. Defaults to programmable for the FIFO selected by the FIFOADR[1:0] pins. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page [+] Feedback ...

Page 27

... TXD1is an active-HIGH output pin from 8051 UART1, which provides the output clock in sync mode, and the output data in async mode. Input N/A RXD0 is the active-HIGH RXD0 input to 8051 UART0, which provides data to the UART in all modes. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page [+] Feedback ...

Page 28

... No Connect. This pin must be left open. N/A N/A No Connect. This pin must be left open. N/A N/A No Connect. This pin must be left open. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description ® chip from suspending interface. Connect to VCC with a 2. peripheral is attached. C-compatible interface. Connect to VCC ...

Page 29

... PL5 PL4 PL3 PL7 PL6 PL5 PL4 PL3 LINE15 LINE14 LINE13 LINE12 LINE11 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access xxxxxxxx RW reserved reserved reserved 00000000 R CLKINV CLKOE 8051RES 00000010 rrbbbbbr GSTATE IFCFG1 IFCFG0 10000000 RW FLAGA2 FLAGA1 FLAGA0 00000000 RW FLAGC2 FLAGC1 FLAGC0 00000000 RW ...

Page 30

... EP4 0 0 EP8 EP6 EP4 EP8 EP6 EP4 EP2 EP1 EP8 EP6 EP4 EP2 EP1 0 EP0ACK HSGRANT URES SUSP CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access LINE2 LINE1 LINE0 00000000 R COL0 LINE17 LINE16 00000000 R LINE10 LINE9 LINE8 00000000 R LINE2 LINE1 LINE0 00000000 R ...

Page 31

... BC4 BC3 BC6 BC5 BC4 BC3 BC6 BC5 BC4 BC3 BC6 BC5 BC4 BC3 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access SUTOK SOF SUDAV 0xxxxxxx rbbbbbbb EP1IN EP0OUT EP0IN 00000000 RW EP1IN EP0OUT EP0IN GPIFWF GPIFDONE 00000000 RW 0 GPIFWF GPIFDONE 000000xx ERRLIMIT 00000000 ...

Page 32

... TERMA1 TERMA0 CTL0E3 CTL0E2 CTL0E1/ CTL0E0/ CTL3 CTL5 CTL4 CTL0E3 CTL0E2 CTL0E1/ CTL0E0/ CTL3 CTL5 CTL4 HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD HOSTATE 0 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access BC2 BC1 BC0 xxxxxxxx RW 0 BUSY STALL 10000000 bbbbbbrb 0 BUSY STALL 00000000 bbbbbbrb 0 BUSY ...

Page 33

... RDY4 RDY3 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access MSTB2 MSTB1 MSTB0 00100000 RW 0 FALLING RISING 00000001 rrrrrrbb 00000010 RW TC26 TC25 TC24 00000000 RW TC18 TC17 TC16 00000000 RW TC10 TC9 TC8 00000000 RW TC2 TC1 TC0 00000001 RW 00000000 RW 0 FS1 FS0 00000000 FIFO2FLAG 00000000 RW x ...

Page 34

... PS1 PT2 PS0 PT1 DONE D15 D14 D13 D12 D11 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access 0 0 400KHZ xxxxxxxx n/a [14 xxxxxxxx 00000111 00000000 RW A10 A9 A8 00000000 00000000 RW A10 A9 A8 00000000 SEL 00000000 IDLE 00110000 RW IT1 IE0 IT0 00000000 00000000 00000000 RW D2 ...

Page 35

... EXEN2 D15 D14 D13 D12 D11 RS1 RS0 1 ERESI RESI INT6 EX6 EX5 PX6 PX5 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default Access xxxxxxxx xxxxxxxx R RB8_1 TI_1 RI_1 00000000 00000000 RW TR2 CT2 CPRL2 00000000 00000000 00000000 00000000 RW D10 D9 D8 00000000 00000000 01000000 RW D2 ...

Page 36

... Temperature Temperature (°C/W) (°C/W) 24.4 23.3 11.9 34.0 15.5 27.7 10.6 14.6 30.9 27.7 θ θ θ Ca) θ CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Parallel Resonant θ Ja Junction to Ambient Temperature θ θ (°C/W) 47.7 45.9 43.2 25.2 58.6 θ θ θ θ Page ...

Page 37

... USB 2.0 compliant in full speed and high speed modes. 10. AC Electrical Characteristics 10.1 USB Transceiver USB 2.0 compliant in full speed and high speed modes. Note 16. Measured at Max VCC, 25°C. Document #: 38-08032 Rev. *M CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Conditions 0< V < VCC OUT I = – ...

Page 38

... ACC1 CL AV DSU t (48 MHz) = 3*t – t – ns. ACC1 CL AV DSU Document #: 38-08032 Rev STBH [18 ACC1 data in Min Typ 20.83 41.66 83 9.6 0 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Max Unit Notes ns 48 MHz ns 24 MHz ns 12 MHz 10 11 Page [+] Feedback ...

Page 39

... Figure 13. Data Memory Read Timing Diagram Stretch = STBH STBL t SCSL t SOEL t [19] DSU ACC1 data in Stretch = 1 [19] t ACC1 Min Typ 20.83 41.66 83.2 9.6 0 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A DSU t DH data in Max Unit Notes ns 48 MHz ns 24 MHz ns 12 MHz 10 11 Page ...

Page 40

... WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for which is based on the stretch value. Document #: 38-08032 Rev. *M Figure 14. Data Memory Write Timing Diagram t t STBH t data out Stretch = 1 data out Min CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A AV OFF1 t OFF1 Max Unit Notes 10.7 ns 11.2 ns 11.2 ns 13 ...

Page 41

... Following is the timing diagram of the read and write strobing function on accessing PORTC. Refer to Section 10.4 for details on propagation delay of RD# and WR# signals. t STBL DATA CAN BE UPDATED BY EXTERNAL LOGIC DATA MUST BE HELD FOR 3 CLK CYLCES t STBL CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Section 10.3 t STBH t STBH Page and [+] Feedback ...

Page 42

... IFCLK must not exceed 48 MHz. Document #: 38-08032 Rev IFCLK t SGA t SRY t RYH valid t t SGD DAH t XCTL N N+1 t XGD Description Min 20.83 8.9 9.2 Description Min. 20.83 2.9 3.7 3.2 4.5 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] [20, 21] Max Unit 7 6.7 ns [21] Max. Unit 200 11 10.7 ns Page ...

Page 43

... Clock to FIFO Data Output Propagation Delay XFD Document #: 38-08032 Rev IFCLK t RDH t SRD t XFLG N N OEon XFD Description Min 20.83 18.7 Description Min 20.83 12.7 3.7 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] t OEoff [21] Max Unit 10.5 ns 10 [21] Max Unit 200 10 ...

Page 44

... OEon t SLOE Turn-off to FIFO Data Hold OEoff Note 23. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz. Document #: 38-08032 Rev RDpwh t RDpwl t XFLG t XFD N N OEon OEoff [23] Description Min CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] Max Unit 10.5 ns 10.5 ns Page [+] Feedback ...

Page 45

... Clock to FLAGS Output Propagation Time XFLG Document #: 38-08032 Rev IFCLK t WRH t SWR SFD FDH t XFLG Description Min 20.83 10.4 9.2 Description Min 20.83 12.1 3.6 3.2 4.5 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] Z [21] Max Unit 9.5 ns [21] Max Unit 200 13.5 ns Page [+] Feedback ...

Page 46

... Clock to FLAGS Output Propagation Delay XFLG Document #: 38-08032 Rev WRpwh t WRpwl t t FDH SFD t XFD Description Min t PEH t SPE t XFLG Description Min 20.83 14.6 Description Min 20.83 8.6 2.5 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] [23] Max Unit [20] [21] Max Unit 9.5 ns [21] Max Unit 200 ...

Page 47

... SFD FDH FDH FDH SFD SFD X-2 X-1 X-3 t PEpwh t PEpwl t XFLG [23] Description Min CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 23 shows this scenario the value [20] t FAH >= t WRH FDH SFD FDH SFD least one IFCLK cycle t SPE t PEH [20] Max Unit ...

Page 48

... Table 30. Slave FIFO Address to Flags/Data Parameters Parameter t FIFOADR[1:0] to FLAGS Output Propagation Delay XFLG t FIFOADR[1:0] to FIFODATA Output Propagation Delay XFD Document #: 38-08032 Rev OEoff t OEon Description Min t XFLG t XFD N N+1 Description Min CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] Max Unit 10.5 ns 10.5 ns [20] Max Unit 10.7 ns 14.3 ns Page [+] Feedback ...

Page 49

... SLRD/SLWR/PKTEND Table 32. Slave FIFO Asynchronous Address Parameters Parameter t FIFOADR[1:0] to SLRD/SLWR/PKTEND Setup Time SFA t RD/WR/PKTEND to FIFOADR[1:0] Hold Time FAH Document #: 38-08032 Rev SFA FAH [21] Description Min 20.83 t FAH t SFA [23] Description Min CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] Max Unit 200 [20] Max Unit Page [+] Feedback ...

Page 50

... FIFO pointer is updated and increments to point to address N+1. For each subsequent rising edge of IFCLK, while (time RDH the SLRD is asserted, the FIFO pointer is incremented and the next data value is placed on the data bus. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] t FAH >= t RDH T=3 ...

Page 51

... AUTOINLEN register). Refer to Figure 23 for further details on this timing. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] t FAH >= t WRH ...

Page 52

... Note In burst read mode, during SLOE is assertion, the data bus driven state and outputs the previous data. After SLRD is asserted, the data from the FIFO is driven on the data bus (SLOE must also be asserted) and then the FIFO pointer is incre- mented. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] t FAH t t ...

Page 53

... SLWR and the PKTEND signal at the before the SFD same time. It should be designed to assert the PKTEND after SLWR is deasserted and met the minimum deasserted pulse width. The FIFOADDR lines have to held constant during the PKTEND assertion. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] t FAH t WRpwl WRpwh T=9 ...

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... CY7C68013A-56PVXC CY7C68013A-56PVXI CY7C68013A-56LFXC CY7C68013A-56LFXI CY7C68015A-56LFXC CY7C68013A-56BAXC CY7C68013A-56LTXC CY7C68013A-56LTXCT CY7C68013A-56LTXI CY7C68014A-56LTXC CY7C68015A-56LTXC CY7C68016A-56LTXC CY7C68016A-56LTXCT Development Tool Kit CY3684 Reference Design Kit CY4611B Document #: 38-08032 Rev. *M CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Package Type RAM Size 128 TQFP – Pb-Free 16K 100 TQFP – Pb-Free 16K 56 SSOP – ...

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... Package Diagrams The FX2LP is available in five packages: 56-pin SSOP ■ 56-pin QFN ■ 100-pin TQFP ■ 128-pin TQFP ■ 56-ball VFBGA ■ Package Diagrams Figure 35. 56-Pin Shrunk Small Outline Package O56 (51-85062) Document #: 38-08032 Rev. *M CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 51-85062-*C Page [+] Feedback ...

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... PACKAGE WEIGHT: 0.162g 4. ALL DIMENSIONS ARE IN MM [MIN/MAX] 5. PACKAGE CODE PART # DESCRIPTION LF56 STANDARD LY56 PB-FREE Figure 37. 56-Pin QFN (Sawn Version) Document #: 38-08032 Rev. *M CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A SIDE VIEW 0.08[0.003] C 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 6.1 0°-12° 0.30[0.012] C SEATING PLANE 0 ...

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... BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS A CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 1.40±0.05 12°±1° A SEE DETAIL (8X) ...

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... BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS A CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 1.40±0.05 12°±1° A SEE DETAIL (8X) ...

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... Connections between the USB connector shell and signal ■ ground must be near the USB connector. Note 24. Source for recommendations: EZ-USB FX2™PCB Design Recommendations, http://www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf and High Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf. Document #: 38-08032 Rev. *M CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A BOTTOM VIEW Ø0. Ø0. Ø0.30±0.05(56X ...

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... Solder Mask Cu Fill Cu Fill 0.013” dia PCB Material This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane Figure 43. X-ray Image of the Assembly CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 43 Page [+] Feedback ...

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... Document History Page Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB FX2LP™ USB Microcontroller High Speed USB Peripheral Controller Document Number: 38-08032 Submission Orig. of REV. ECN NO. Date Change ** 124316 03/17/03 VCS *A 128461 09/02/03 VCS *B 130335 10/09/03 KKV *C 131673 02/12/04 KKU *D 230713 ...

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... Removed T0OUT and T1OUT from CY7C68015A/16A Updated t Min value in Figure 20 SWR Updated 56-lead QFN package diagram Added 56-Pin QFN ( mm) package diagram Updated ordering information for CY7C68013A-56LTXC, CY7C68013A-56LTXI, CY7C68014A-56LTXC, CY7C68015A-56LTXC, and CY7C68016A-56LTXC parts. PSoC Solutions General psoc.cypress.com Low Power/Low Voltage clocks.cypress.com Precision Analog LCD Drive CAN 2 ...

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