IC MCU 8K USB LS MCU 24-SOIC

 

CY7C63613-SC

Manufacturer Part NumberCY7C63613-SC
DescriptionIC MCU 8K USB LS MCU 24-SOIC
ManufacturerCypress Semiconductor Corp
SeriesM8™
CY7C63613-SC datasheets

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Specifications of CY7C63613-SC

ApplicationsUSB MicrocontrollerCore ProcessorM8B
Program Memory TypeOTP (8 kB)Controller SeriesCY7C636xx
Ram Size256 x 8InterfacePS2, USB
Number Of I /o16Voltage - Supply4 V ~ 5.5 V
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case24-SOIC (7.5mm Width)Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names428-1321  
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10.1
USB Enumeration
The enumeration sequence is shown below:
1. The host computer sends a Setup packet followed by a Data packet to USB address 0 requesting the Device descriptor.
2. The USB Controller decodes the request and retrieves its Device descriptor from the program memory space.
3. The host computer performs a control read sequence and the USB Controller responds by sending the Device descriptor over
the USB bus.
4. After receiving the descriptor, the host computer sends a Setup packet followed by a Data packet to address 0 assigning a
new USB address to the device.
5. The USB Controller stores the new address in its USB Device Address Register after the no-data control sequence is complete.
6. The host sends a request for the Device descriptor using the new USB address.
7. The USB Controller decodes the request and retrieves the Device descriptor from the program memory.
8. The host performs a control read sequence and the USB Controller responds by sending its Device descriptor over the USB bus.
9. The host generates control reads to the USB Controller to request the Configuration and Report descriptors.
10.The USB Controller retrieves the descriptors from its program space and returns the data to the host over the USB.
10.2
PS/2 Operation
PS/2 operation is possible with the CY7C636xx series through the use of firmware and several operating modes. The first enabling
feature:
1. USB Bus reset on D+ and D is an interrupt that can be disabled;
2. USB traffic can be disabled via bit 7 of the USB register;
3. D+ and D can be monitored and driven via firmware as independent port bits.
Bits 5 and 4 of the Upstream Status and Control register are directly connected to the D+ and D USB pins of the CY7C636xx.
These pins constantly monitor the levels of these signals with CMOS input thresholds. Firmware can poll and decode these signal s
as PS/2 clock and data.
Bits [2:0] defaults to ‘000’ at reset which allows the USB SIE to control output on D+ and D . Firmware can override the SIE and
directly control the state of these pins via these 3 control bits. Since PS/2 is an open drain signaling protocol, these modes allow
all 4 PS/2 states to be generated on the D+ and D pins
10.3
USB Port Status and Control
USB status and control is regulated by the USB Status and Control Register located at I/O address 0x1Fh as shown in Figure
10-1 . This is a read/write register. All reserved bits must be written to zero. All bits in the register are cleared during reset.
7
6
Reserved
Reserved
Figure 10-1. USB Status and Control Register 0x1Fh
The Bus Activity bit is a “sticky” bit that indicates if any non-idle USB event has occurred on the USB bus. The user firmware
should check and clear this bit periodically to detect any loss of bus activity. Writing a “0” to the Bus Activity bit clears it while
writing a “1” preserves the current value. In other words, the firmware can clear the Bus Activity bit, but only the SIE can set it.
The 1.024-ms timer interrupt service routine is normally used to check and clear the Bus Activity bit. The following table shows
how the control bits are encoded for this register.
FOR
PRELIMINARY
5
4
3
R
R
R/W
D+
D–
Bus Activity
18
CY7C63612/13
2
1
0
R/W
R/W
R/W
Control
Control
Control
Bit 2
Bit 1
Bit 0

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