IC MCU 8K USB LS MCU 24-SOIC

 

CY7C63613-SC

Manufacturer Part NumberCY7C63613-SC
DescriptionIC MCU 8K USB LS MCU 24-SOIC
ManufacturerCypress Semiconductor Corp
SeriesM8™
CY7C63613-SC datasheets

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Specifications of CY7C63613-SC

ApplicationsUSB MicrocontrollerCore ProcessorM8B
Program Memory TypeOTP (8 kB)Controller SeriesCY7C636xx
Ram Size256 x 8InterfacePS2, USB
Number Of I /o16Voltage - Supply4 V ~ 5.5 V
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case24-SOIC (7.5mm Width)Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names428-1321  
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incremented. The second byte is stored in memory addressed by the program stack pointer and the PSP is incremented again.
The net effect is to store the program counter and flags on the program “stack” and increment the program stack pointer by two.
The Return From Interrupt (RETI) instruction decrements the program stack pointer, then restores the second byte from memory
addressed by the PSP. The program stack pointer is decremented again and the first byte is restored from memory addressed
by the PSP. After the program counter and flags have been restored from stack, the interrupts are enabled. The effect is to restore
the program counter and flags from the program stack, decrement the program stack pointer by two, and re-enable interrupts.
The Call Subroutine (CALL) instruction stores the program counter and flags on the program stack and increments the PSP by two.
The Return From Subroutine (RET) instruction restores the program counter, but not the flags, from program stack and decre-
ments the PSP by two.
4.5
8-bit Data Stack Pointer (DSP)
The Data Stack Pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH
instruction will pre-decrement the DSP, then write data to the memory location addressed by the DSP. A POP instruction will rea d
data from the memory location addressed by the DSP, then post-increment the DSP.
During a reset, the Data Stack Pointer will be set to zero. A PUSH instruction when DSP equal zero will write data at the top of
the data RAM (address 0xFF). This would write data to the memory area reserved for a FIFO for USB endpoint 0. In non-USB
applications, this works fine and is not a problem. For USB applications, it is strongly recommended that the DSP is loaded after
reset just below the USB DMA buffers.
4.6
Address Modes
The CY7C63612/13 microcontrollers support three addressing modes for instructions that require data operands: data, direct,
and indexed.
4.6.1
Data
The “Data” address mode refers to a data operand that is actually a constant encoded in the instruction. As an example, consider
the instruction that loads A with the constant 0xE8h:
• MOV A,0E8h
This instruction will require two bytes of code where the first byte identifies the “MOV A” instruction with a data operand as the
second byte. The second byte of the instruction will be the constant “0xE8h”. A constant may be referred to by name if a prior
“EQU” statement assigns the constant value to the name. For example, the following code is equivalent to the example shown
above:
• DSPINIT: EQU 0E8h
• MOV A,DSPINIT
4.6.2
Direct
“Direct” address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the
variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address
location 0x10h:
• MOV A, [10h]
In normal usage, variable names are assigned to variable addresses using “EQU” statements to improve the readability of the
assembler source code. As an example, the following code is equivalent to the example shown above:
• buttons: EQU 10h
• MOV A,[buttons]
4.6.3
Indexed
“Indexed” address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is
the sum of a constant encoded in the instruction and the contents of the “X” register. In normal usage, the constant will be the
“base” address of an array of data and the X register will contain an index that indicates which element of the array is actually
addressed:
• array: EQU 10h
• MOV X,3
• MOV A,[x+array]
This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10h. The fourth
element would be at address 0x13h.
FOR
PRELIMINARY
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CY7C63612/13

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