CY7C64013-SC Cypress Semiconductor Corp, CY7C64013-SC Datasheet
CY7C64013-SC
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... Full-Speed USB (12-Mbps) Function Cypress Semiconductor Corporation Document #: 38-08001 Rev. *A • 3901 North First Street • CY7C64013 CY7C64113 , San Jose CA 95134 • 408-943-2600 Revised January 30, 2004 ...
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... C-COMPATIBLE CONTROLLER .............................................................................................. 24 14.0 HARDWARE ASSISTED PARALLEL INTERFACE (HAPI) ........................................................ 25 15.0 PROCESSOR STATUS AND CONTROL REGISTER ................................................................ 26 16.0 INTERRUPTS ............................................................................................................................... 27 16.1 Interrupt Vectors ..................................................................................................................... 29 16.2 Interrupt Latency ..................................................................................................................... 29 16.3 USB Bus Reset Interrupt ......................................................................................................... 30 16.4 Timer Interrupt ........................................................................................................................ 30 16.5 USB Endpoint Interrupts ......................................................................................................... 30 Document #: 38-08001 Rev. *A TABLE OF CONTENTS CY7C64013 CY7C64113 Page ...
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... REGISTER SUMMARY ................................................................................................................ 42 21.0 SAMPLE SCHEMATIC ................................................................................................................ 43 22.0 ABSOLUTE MAXIMUM RATINGS .............................................................................................. 44 23.0 ELECTRICAL CHARACTERISTICS FOSC = 6 MHZ; OPERATING TEMPERATURE = 0 TO 70°C, V 24.0 SWITCHING CHARACTERISTICS 25.0 ORDERING INFORMATION ........................................................................................................ 48 26.0 PACKAGE DIAGRAMS ............................................................................................................... 48 Document #: 38-08001 Rev. *A TABLE OF CONTENTS = 4.0V TO 5.25V ....................... 44 CC ....................................................................... 6.0 MHz) OSC CY7C64013 CY7C64113 Page ...
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... Figure 18-5. Token/Data Packet Flow Diagram..................................................................................... 38 Figure 24-1. Clock Timing...................................................................................................................... 47 Figure 24-2. USB Data Signal Timing.................................................................................................... 47 Figure 24-3. HAPI Read by External Interface from USB Microcontroller ............................................. 47 Figure 24-4. HAPI Write by External Device to USB Microcontroller..................................................... 48 Document #: 38-08001 Rev. *A LIST OF FIGURES CY7C64013 CY7C64113 Page ...
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... Table 16-1. Interrupt Vector Assignments ............................................................................................ 31 Table 17-1. Control Bit Definition for Upstream Port ............................................................................ 34 Table 18-1. Memory Allocation for Endpoints ...................................................................................... 35 Table 19-1. USB Register Mode Encoding ........................................................................................... 39 Table 19-2. Details of Modes for Differing Traffic Conditions ............................................................... 41 Document #: 38-08001 Rev. *A LIST OF TABLES CY7C64013 CY7C64113 Page ...
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... Integrated USB transceivers • Improved output drivers to reduce EMI • Operating voltage from 4.0V to 5.5V DC • Operating temperature from degrees Celsius — CY7C64013 available in 28-pin SOIC and 28-pin PDIP packages — CY7C64113 available in 48-pin SSOP packages • Industry-standard programmer support Document #: 38-08001 Rev. *A ...
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... GPIO The CY7C64013 features 19 GPIO pins to support USB and other applications. The I/O pins are grouped into three ports (P0[7:0], P1[2:0], P2[6:2], P3[2:0]) where each port can be configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs ...
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... P2[4]; STB P2[5]; OE P2[6]; CS High Current P3[2:0] Outputs GPIO Additional PORT 3 P3[7:3] High Current Outputs DAC[0] DAC DAC[2] PORT DAC[7] CY7C64113 only SCLK SDATA Interface 2 *I C-compatible interface enabled by firmware through P2[1:0] or P1[1:0] CY7C64013 CY7C64113 D+[0] Upstream USB Port D–[0] Page ...
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... REF 4 P3[0] P1[1] 25 P3[2] GND 5 24 P2[2] P3[ GND D+[ P2[4] D–[ P2[ P2[6] 19 P2[ P0[7] 18 P0[0] P0[ P0[2] P0[3] 13 P0[4] 16 P0[ P0[6] CY7C64013 CY7C64113 CY7C64113 48-pin SSOP XTALOUT P1[1] XTALIN 3 46 P1[0] V REF 4 P1[2] P1[3] 45 P1[4] P1[ P1[6] P1[ P3[0] P3[ P3[2] D+[ D–[ GND P3[ P3[4] GND ...
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... GPIO Port 1 Data 0x02 R/W GPIO Port 2 Data 0x03 R/W GPIO Port 3 Data 0x04 W Interrupt Enable for Pins in Port 0 0x05 W Interrupt Enable for Pins in Port 1 0x06 W Interrupt Enable for Pins in Port 2 0x07 W Interrupt Enable for Pins in Port 3 CY7C64013 CY7C64113 Description Function Page Page ...
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... R/W USB Address A, Endpoint 4 Configuration 0x48 Reserved 0x49 Reserved 0x4A Reserved 0x4B Reserved 0x4C Reserved 0x4D Reserved 0x4E Reserved 0x4F Reserved 0x50 Reserved 0x51 Reserved 0xFF R/W Microprocessor Status and Control Register CY7C64013 CY7C64113 Function 2 C Position Configuration Page Page ...
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... IOWX [X+expr CPL 1B 6 ASL 1C 4 ASR 1D 5 RLC 1E RRC 1F 4 RET RETI 10 JC 80-8F 5 JNC 90-9F 10 JACC A0-AF 5 INDEX B0-BF 5 CY7C64013 CY7C64113 MNEMONIC operand opcode 20 acc direct 23 index 24 acc direct 27 index 28 address 29 address direct 31 index 32 direct 33 index 34 direct 35 index ...
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... CALL instruction. The program counter, carry flag, and zero flag are restored from the program stack during a RETI instruction. Only the program counter is restored during a RET instruction. The program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from location 0x00 and up. Document #: 38-08001 Rev. *A CY7C64013 CY7C64113 Page ...
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... USB address A endpoint 3 interrupt vector 0x0010 USB address A endpoint 4 interrupt vector 0x0012 Reserved 0x0014 DAC interrupt vector 0x0016 GPIO interrupt vector 2 0x0018 I C interrupt vector 0x001A Program Memory begins here 0x1FDF 8 KB (-32) PROM ends here (CY7C64013, CY7C64113) CY7C64013 CY7C64113 Page ...
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... Refer to Section 5.5 for a description of DSP. 2. Endpoint sizes are fixed by the Endpoint Size Bit (I/O register 0x1F, Bit 7), see Table 18-1. Document #: 38-08001 Rev. *A Address 0x00 Program Stack Growth user selected User variables USB FIFO space for five endpoints 0xFF CY7C64013 CY7C64113 Data Stack Growth [2] Page ...
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... Move 20 hex into Accumulator (must be D8h or less) SWAP A,DSP ; swap accumulator value into DSP register 5.6 Address Modes The CY7C64013 and CY7C64113 microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed. 5.6.1 Data (Immediate) “Data” address mode refers to a data operand that is actually a constant encoded in the instruction example, consider the instruction that loads A with the constant 0xD8: • ...
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... XTALIN (pin Figure 6-1. Clock Oscillator On-Chip Circuit to stabilize at a valid operating voltage before the chip executes code. CC drops below approximately 2.5V, and remains asserted until V CC CY7C64013 CY7C64113 To Internal PLL has risen above approximately CC rises above this level CC level is CC ...
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... Write to Status and Control Register - Enter suspend, wait for USB activity (or GPIO Interrupt) nop ; This executes before any ISR ... ; Remaining code for exiting suspend routine Document #: 38-08001 Rev WATCH No write to WDT Execution begins at register, so WDR Reset Vector 0x0000 goes HIGH Figure 7-1. Watchdog Reset (WDR) CY7C64013 CY7C64113 or Gnd. This also CC Page ...
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... P1.5 P1.4 P1.3 R/W R/W R Figure 9-3. Port 1 Data P2.5 P2.4 P2.3 R/W R/W R Figure 9-4. Port 2 Data CY7C64013 CY7C64113 Q2 GPIO PIN *Port 0,1,2: Low I sink Port 3: High I sink ADDRESS 0x00 2 1 P0.2 P0.1 R/W R ADDRESS 0x01 2 1 P1.2 P1.1 R/W ...
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... Therefore unused port bit is programmed in open-drain mode, it must be written with a ‘0.’ Notice that the CY7C64013 part always requires that the data bits P1[7:3], P2[7,1,0], and P3[7:3] be written with a ‘0.’ In normal non-HAPI mode, reads from a GPIO port always return the present state of the voltage at the pin, independent of the settings in the Port Data Registers. If HAPI mode is activated for a port, reads of that port return latched data as controlled by the HAPI signals (see Section 14.0). During reset, all of the GPIO pins are set to a high-impedance input state (‘ ...
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... Figure 9-8. Port 1 Interrupt Enable Figure 9-9. Port 2 Interrupt Enable Figure 9-10. Port 3 Interrupt Enable DAC to sink current to drive the output LOW. Figure 10-1 shows a block diagram of the sink CY7C64013 CY7C64113 P1.2 Intr Enable P1.1 Intr Enable P1.0 Intr Enable ...
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... DAC Read to Interrupt Controller Figure 10-1. Block Diagram of a DAC Pin 5 4 Reserved Reserved Reserved R/W R Figure 10-2. DAC Port Data 5 4 Reserved Reserved - - Figure 10-3. DAC Sink Register CY7C64013 CY7C64113 kΩ DAC I/O Pin DAC[2] DAC[1] R/W R/W R ADDRESS 0x38 -0x3F 3 2 ...
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... Figure 10-4. DAC Port Interrupt Enable Reserved Reserved Reserved Figure 10-5. DAC Port Interrupt Polarity Timer Bit 5 Timer Bit 4 Timer Bit Figure 11-1. Timer LSB Register CY7C64013 CY7C64113 ADDRESS 0x31 Enable Bit 2 Enable Bit 1 Enable Bit ADDRESS 0x32 Enable Bit 2 Enable Bit 1 Enable Bit ...
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... C-compatible interface and HAPI functions, discussed in detail in Sections 13.0 and 5 4 LEMPTY DRDY Latch Polarity Polarity Empty R/W R Figure 12-1. HAPI/I C Configuration Register 2 C-compatible options exist due to pin limitations in certain 2 C-compatible operation. CY7C64013 CY7C64113 Timer Bit 10 Timer Bit 1.024-ms Interrupt µ 128- s Interrupt 1 0 1-MHz Clock ...
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... R Figure 13- Data Register 5 4 Xmit Mode ACK Addr R/W R/W R Figure 13- Status and Control Register CY7C64013 CY7C64113 Position P2[1:0], 0:SCL, 1:SDA P1[1:0], 0:SCL, 1:SDA P2[1:0], 0:SCL, 1:SDA 2 C Status and Control Register 2 C Status and Control 2 C SDA data is connected to bit 1 of GPIO port ...
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... C Stop bit is generated Status and Control register. This locking allows the hardware restart sequence. The I C target address for the restart must be written to the data register before CY7C64013 CY7C64113 Description 2 C GPIO pins 2 C Stop bit detected (unless firmware did not ...
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... If 1, Data Ready is active HIGH, DReadyPin is active LOW. Determines polarity of Latch Empty bit and LatEmptyPin Latch Empty is active LOW, LatEmptyPin is active HIGH Latch Empty is active HIGH, LatEmptyPin is active LOW. CY7C64013 CY7C64113 C-compatible bus, e.g. in receive mode if firmware 2 C-compatible pins. When this bit is cleared, these ...
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... Watchdog Reset (bit 6 set) has occurred and no interrupts are pending (bit 7 clear). The Watchdog Reset does not effect the state of the POR and the Bus Reset Interrupt bits. Document #: 38-08001 Rev USB Bus Reset Power-On Suspend Interrupt Reset R/W R/W R CY7C64013 CY7C64113 ADDRESS 0xFF Interrupt Reserved Run Enable Sense R R/W R Page ...
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... GPIO Interrupt DAC Interrupt Reserved Enable enable R Figure 16-1. Global Interrupt Enable Register 5 4 Reserved EPB1 Interrupt EPB0 Interrupt Enable Enable - R CY7C64013 CY7C64113 1.024-ms 128-µs Interrupt Interrupt Enable Enable R/W R/W R EPA2 Interrupt EPA1 Interrupt Enable Enable R/W R/W ...
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... Bit AddrB EP1 CLR AddrB EP1 IRQ CLR Hub CLR Hub IRQ Interrupt DAC CLR DAC IRQ Acknowledge GPIO CLR GPIO IRQ CLR IRQ Interrupt Priority Encoder CY7C64013 CY7C64113 IRQ Sense IRQ Int Enable Sense Controlled by DI, EI, and RETI Instructions Page ...
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... USB Address A Endpoint 1 interrupt 0x000C USB Address A Endpoint 2 interrupt 0x000E USB Address A Endpoint 3 interrupt 0x0010 USB Address A Endpoint 4 interrupt 0x0012 0x0014 0x0016 0x0018 CY7C64013 CY7C64113 Function USB Bus Reset interrupt 128-µs timer interrupt 1.024-ms timer interrupt Reserved DAC interrupt GPIO interrupt 2 I ...
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... Global 1 = Enable GPIO Interrupt 0 = Disable Enable (Bit 5, Register 0x20) Figure 16-4. GPIO Interrupt Structure 2 C-compatible bus to signal the need for firmware interaction. This generally CY7C64013 CY7C64113 GPIO Interrupt Flip Flop Interrupt Priority Encoder CLR 2 C registers. Refer to Section 13.0 for details on ...
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... USB status and control is regulated by the USB Status and Control Register, as shown in Figure 17-1. All bits in the register are cleared during reset. Document #: 38-08001 Rev C-compatible hardware in the idle state interrupt occurs. ) must be placed in series with the D+ and D– lines, as close to ext CY7C64013 CY7C64113 2 C register contents may be Page ...
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... D+ Upstream D– Upstream Bus Activity Figure 17-1. USB Status and Control Register 5 4 Device Address Device Address Device Address Bit 5 Bit 4 R/W R Figure 18-1. USB Device Address Registers CY7C64013 CY7C64113 Control Action Control Action Bit 2 Bit 1 R/W R/W R ADDRESSES Device Address ...
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... Size Label 0xA8 8 EPA4 0xB0 8 EPA3 0xB8 8 EPA2 0xC0 32 EPA1 0xE0 32 EPA0 Endpoint 0 OUT ACK Received R/W R CY7C64013 CY7C64113 [0,1] [1,1] Start Start Address Size Label Address 0xD8 8 EPA4 0xB0 0xE0 8 EPA3 0xA8 0xE8 8 EPA0 0xB8 0xF0 8 EPA1 0xC0 0xF8 8 EPA2 ...
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... ACK Mode Bit 3 R/W R Byte Count Bit 5 Byte Count Bit 4 Byte Count Bit 3 Byte Count Bit 2 Byte Count Bit 1 Byte Count Bit 0 R/W R Figure 18-4. USB Endpoint Counter Registers CY7C64013 CY7C64113 ADDRESSES 0x14, 0x16, 0x42 Mode Bit 2 Mode Bit 1 R/W R/W R ...
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... For details on what conditions are required to generate an endpoint interrupt, refer to Table 19-2. 4. The contents of the updated endpoint 0 mode and counter registers are locked, except the SETUP bit of the endpoint 0 mode register which was locked earlier. Document #: 38-08001 Rev. *A CY7C64013 CY7C64113 Page ...
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... Data Packet UPDATE Host To Device Data 1/0 Data Packet SETUP Host To Device Data 1/0 Data Packet Figure 18-5. Token/Data Packet Flow Diagram CY7C64013 CY7C64113 Host To Device Hand Shake Packet UPDATE Device To Host ACK NAK STAL 16 C Hand Shake UPDATE Packet UPDATE only if FIFO is ...
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... On issuance of an ACK this mode is changed by SIE to 1100 stall ignore (NAK In) NAK check Is set by SIE on an ACK from mode 1111 (Ack In - Status Out) TX Count check On issuance of an ACK this mode is changed by SIE to 1110 (NAK In - Status Out) CY7C64013 CY7C64113 Comments Page ...
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... DTOG DVAL COUNT Setup Byte Count (bits 0..5, Figure 17-4) Data Valid (bit 6, Figure 17-4) Data0/1 (bit7 Figure 17-4) (Bit[7..5], Figure 17-2) The validity of the received data CY7C64013 CY7C64113 In Out ACK Response SIE’s Response to the Host PID Status Bits ...
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... Changes made by SIE to Internal Registers and Mode Bits dval DTOG DVAL COUNT Setup valid 1 1 updates UC valid 0 1 updates UC valid updates 1 updates invalid valid 1 1 updates UC CY7C64013 CY7C64113 In Out ACK Mode Bits Response ACK NoChange ignore NoChange ignore In Out ACK Mode Bits Response NoChange ignore NoChange NAK NoChange ...
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... updates updates updates updates Changes made by SIE to Internal Registers and Mode Bits dval DTOG DVAL COUNT Setup CY7C64013 CY7C64113 Stall Stall NoChange ignore NoChange ignore NoChange NAK NoChange ACK Stall Stall NoChange ignore NoChange ignore Stall In Out ACK Mode Bits ...
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... Mode Bit 2 IN OUT Received Received Data Valid Byte Count Byte Count Byte Count Byte Count Bit 5 Bit 4 Bit ACK Mode Bit 3 Mode Bit 2 CY7C64013 CY7C64113 Read/Write/ Bit 2 Bit 1 Bit 0 Both/- P0.2 P0.1 P0.0 BBBBBBBB P1.2 P1.1 P1.0 BBBBBBBB P2.2 P2.1 P2.0 BBBBBBBB P3 ...
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... UUP Vbus 22x2(R ) ext SHELL D0- D0+ 4.7 nF 250VAC XTALO 10M XTALI 6.000 MHz GND 0V GND Vpp 0V CY7C64013 CY7C64113 Read/Write/ Bit 2 Bit 1 Bit 0 Both/- Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ...
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... Gnd 1.5 kΩ ± REF Including R Resistor ext All ports, LOW to HIGH edge All ports, HIGH to LOW edge 1.9 mA (all ports 0,1,2, below approximately 2.5V. CC CY7C64013 CY7C64113 Min. Max. 3.15 3.45 –0.4 0 0.2 0.8 2.5 0.8 2.0 20 –10 ...
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... DAC Port (f = 6.0 MHz) OSC Description Clock Source [9] USB Full Speed Signaling / DAC Interface HAPI Read Cycle Timing [10, 11] [11] [10, 11] HAPI Write Cycle Timing [11] [11] [10, 11] Timer Signals CY7C64013 CY7C64113 Min. Max. Unit 8.0 24.0 kΩ 0.1 0.3 mA 0.5 1.5 mA 1.6 4 ...
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... Internal Write Internal Addr Figure 24-3. HAPI Read by External Interface from USB Microcontroller Document #: 38-08001 Rev CYC Figure 24-1. Clock Timing t r 90% 90% 10% Figure 24-2. USB Data Signal Timing t OED t OEDR (Ready) Port0 CY7C64013 CY7C64113 t r 10% Int t RD D[23:0] t OEZ Page ...
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... STB (P2.4, input) DATA (input) OE (P2.5, input) LEmptyPin (P2.2, output) (Shown for LEMPTY Polarity=0) Internal Read Internal Addr Figure 24-4. HAPI Write by External Device to USB Microcontroller 25.0 Ordering Information Ordering Code PROM Size CY7C64013- CY7C64013- CY7C64113-PVC 8 KB Document #: 38-08001 Rev D[23:0] t DSTB ...
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... SEATING PLANE 1.370[34.79] 1.425[36.19] 0.120[3.05] 0.140[3.55] 0.015[0.38] 0.060[1.52] 0.055[1.39] 0.065[1.65] 0.015[0.38] 0.020[0.50] CY7C64013 CY7C64113 MIN. DIMENSIONS IN INCHES[MM] MAX. REFERENCE JEDEC MO-095 PART # P28.3 STANDARD PKG. PZ28.3 LEAD FREE PKG. 0.290[7.36] 0.325[8.25] 0.009[0.23] 3° MIN. 0.012[0.30] 0.310[7.87] 0.385[9.78] ...
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... Molded SOIC S21 PIN DIMENSIONS IN INCHES[MM] * 0.394[10.01] REFERENCE JEDEC MO-119 0.419[10.64] 0.291[7.39] PACKAGE WEIGHT 0.85gms 0.300[7.62] 28 0.026[0.66] 0.032[0.81] SEATING PLANE 0.092[2.33] 0.105[2.67] 0.004[0.10] * 0.004[0.10] 0.0118[0.30] CY7C64013 CY7C64113 MIN. MAX. PART # S28.3 STANDARD PKG. SZ28.3 LEAD FREE PKG. * 0.0091[0.23] 0.015[0.38] 0.0125[3.17] 0.050[1.27] 51-85026-*C Page ...
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... Document History Page Document Title: CY7C64013, CY7C64113 Full-Speed USB (12 Mbps) Function Document Number: 38-08001 Issue REV. ECN NO. Date ** 109962 12/16/01 *A 129715 02/05/04 Document #: 38-08001 Rev. *A Orig. of Change SZV Change from Spec number: 38-00626 to 38-08001 MON Added register bit definitions Added default bit state of each register ...