CY7C66113-PVC Cypress Semiconductor Corp, CY7C66113-PVC Datasheet

IC MCU 8K USB HUB 4 PORT 56TSSOP

CY7C66113-PVC

Manufacturer Part Number
CY7C66113-PVC
Description
IC MCU 8K USB HUB 4 PORT 56TSSOP
Manufacturer
Cypress Semiconductor Corp
Datasheets

Specifications of CY7C66113-PVC

Applications
USB Hub/Microcontroller
Core Processor
M8
Program Memory Type
OTP (8 kB)
Controller Series
USB Hub
Ram Size
256 x 8
Interface
I²C, USB, HAPI
Number Of I /o
31
Voltage - Supply
4 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-SSOP
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
56
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
428-1330

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C66113-PVC
Manufacturer:
CY
Quantity:
10
Cypress Semiconductor Corporation
Document #: 38-08024 Rev. *A
Full-Speed USB (12 Mbps) Peripheral
Controller with Integrated Hub
3901 North First Street
San Jose
,
CA 95134
Revised March 6, 2003
CY7C66013
CY7C66113
408-943-2600

Related parts for CY7C66113-PVC

CY7C66113-PVC Summary of contents

Page 1

... Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub Cypress Semiconductor Corporation Document #: 38-08024 Rev. *A • 3901 North First Street • CY7C66013 CY7C66113 , San Jose CA 95134 • 408-943-2600 Revised March 6, 2003 ...

Page 2

... DAC Isink Registers ................................................................................................................ 23 10.2 DAC Port Interrupts ................................................................................................................. 23 11.0 12-BIT FREE-RUNNING TIMER .................................................................................................. AND HAPI CONFIGURATION REGISTER ............................................................................ 24 2 13.0 I C-COMPATIBLE CONTROLLER .............................................................................................. 25 14.0 HARDWARE ASSISTED PARALLEL INTERFACE (HAPI) ........................................................ 27 15.0 PROCESSOR STATUS AND CONTROL REGISTER ................................................................ 28 Document #: 38-08024 Rev. *A TABLE OF CONTENTS CY7C66013 CY7C66113 Page ...

Page 3

... Endpoint Mode/Count Registers Update and Locking Mechanism ......................................... 42 20.0 USB MODE TABLES ................................................................................................................... 44 21.0 REGISTER SUMMARY ................................................................................................................ 48 22.0 SAMPLE SCHEMATIC ................................................................................................................ 51 23.0 ABSOLUTE MAXIMUM RATINGS .............................................................................................. 52 24.0 ELECTRICAL CHARACTERISTICS ............................................................................................ 52 25.0 SWITCHING CHARACTERISTICS 26.0 ORDERING INFORMATION ........................................................................................................ 55 27.0 PACKAGE DIAGRAMS ............................................................................................................... 56 Document #: 38-08024 Rev. *A TABLE OF CONTENTS (continued) (f OSC = 6.0 MHz) ...................................................................................... 53 CY7C66013 CY7C66113 Page ...

Page 4

... Figure 19-5. Token/Data Packet Flow Diagram .................................................................................... 43 Figure 22-1. Sample Schematic ........................................................................................................... 51 Figure 25-1. Clock Timing ..................................................................................................................... 54 Figure 25-2. USB Data Signal Timing ................................................................................................... 54 Figure 25-3. HAPI Read by External Interface from USB Microcontroller ............................................ 54 Figure 25-4. HAPI Write by External Device to USB Microcontroller .................................................... 55 Document #: 38-08024 Rev. *A LIST OF FIGURES CY7C66013 CY7C66113 Page ...

Page 5

... Table 20-1. USB Register Mode Encoding ........................................................................................... 44 Table 20-2. Decode Table for Table 20-3: “Details of Modes for Differing Traffic Conditions” ............. 45 Table 20-3. Details of Modes for Differing Traffic Conditions (see Table 20-2 for the decode legend) 46 Document #: 38-08024 Rev. *A LIST OF TABLES CY7C66013 CY7C66113 Page ...

Page 6

... Higher current drive achievable by connecting multiple GPIO pins together to drive a common output — Each GPIO port can be configured as inputs with internal pull-ups or open drain outputs or traditional CMOS outputs — A Digital-to-Analog Conversion (DAC) port with programmable current sink outputs is available on the CY7C66113 device — ...

Page 7

... Functional Overview The CY7C66013 and CY7C66113 are compound devices with a full-speed USB microcontroller in combination with a USB hub. Each device is well-suited for combination peripheral functions with hubs, such as a keyboard hub function. The eight-bit one-time-programmable microcontroller with a 12-Mbps USB Hub supports as many as four downstream ports. ...

Page 8

... USB The CY7C66013 and CY7C66113 include an integrated USB Serial Interface Engine (SIE) that supports the integrated periph- erals and the hub controller function. The hardware supports up to two USB device addresses with one device address for the hub (two endpoints) and a device address for a compound device (three endpoints). The SIE allows the USB host to communicate with the hub and functions integrated into the microcontroller ...

Page 9

... P2[6]; CS P3[0] GPIO High Current Outputs PORT 3 P3[4] GPIO Additional P3[5] High Current PORT 3 P3[6] Outputs DAC[0] DAC PORT DAC[7] CY7C66113 only SCLK SDATA Interface 2 *I C-compatible interface enabled by firmware through P2[1:0] or P1[1:0] CY7C66013 CY7C66113 D+[0] Upstream USB Port D–[0] USB D+[1] D– ...

Page 10

... D–[4] D+[ D+[4] D–[ P2[0] P2[1] 16 D+[2] 33 P2[ GND D–[ P2[4] P2[ P2[6] P2[ P2[ P0[0] DAC[ P0[2] P0[ P0[4] P0[ P0[6] P0[3] P0[1] DAC[5] DAC[3] DAC[1] CY7C66013 CY7C66113 CY7C66113 56-pin SSOP P1[ P1[0] 4 P1[2] 53 P1[ P1[ P3[ D–[ D+[ P3[ P3[ D–[ D+[ P3[ P2[ P2[ GND 18 39 ...

Page 11

... R/W GPIO Port 2 Data R/W GPIO Port 3 Data W Interrupt Enable for Pins in Port 0 W Interrupt Enable for Pins in Port 1 Interrupt Enable for Pins in Port 2 W Interrupt Enable for Pins in Port 3 W R/W GPIO Port Configurations CY7C66013 CY7C66113 Description Function Page Page ...

Page 12

... Hub Downstream Ports Control Hub Downstream Port Suspend Control R/W Hub Downstream Ports Resume Status R R Hub Downstream Ports SE0 Status R Hub Downstream Ports Differential data R/W Hub Downstream Ports Force LOW R/W Microprocessor Status and Control Register CY7C66013 CY7C66113 Function Page ...

Page 13

... AND [expr],A 5 AND [X+expr],A 7 XOR [expr],A 8 XOR [X+expr],A 4 IOWX [X+expr] 5 CPL 6 ASL 4 ASR 5 RLC RRC 4 RET RETI JNC 10 JACC 5 INDEX 5 CY7C66013 CY7C66113 operand opcode cycles 20 4 acc direct 23 7 index 24 8 acc direct 27 7 index 28 8 address 29 5 address 2A 5 ...

Page 14

... CALL instruction. The program counter, carry flag, and zero flag are restored from the program stack during a RETI instruction. Only the program counter is restored during a RET instruction. The program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from location 0x00 and up. Document #: 38-08024 Rev. *A CY7C66013 CY7C66113 Page ...

Page 15

... USB address B endpoint 0 interrupt vector 0x0010 USB address B endpoint 1 interrupt vector 0x0012 Hub interrupt vector 0x0014 DAC interrupt vector GPIO interrupt vector 0x0016 2 0x0018 I C interrupt vector 0x001A Program Memory begins here 0x1FDF 8 KB (-32) PROM ends here (CY7C66013, CY7C66113) CY7C66013 CY7C66113 Page ...

Page 16

... Endpoint sizes are fixed by the Endpoint Size Bit (I/O register 0x1F, Bit 7), see Table 19-1. Document #: 38-08024 Rev. *A Address 0x00 user selected User variables USB FIFO space for up to two Addresses and five endpoints 0xFF CY7C66013 CY7C66113 Program Stack Growth Data Stack Growth Page [2] ...

Page 17

... Move 20 hex into Accumulator (must be D8h or less) SWAP A,DSP ; swap accumulator value into DSP register. 5.6 Address Modes The CY7C66013 and CY7C66113 microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed. 5.6.1 Data (Immediate) “Data” address mode refers to a data operand that is actually a constant encoded in the instruction example, consider the instruction that loads A with the constant 0xD8: • ...

Page 18

... WATCH No write to WDT register, so WDR goes HIGH Figure 7-1. Watchdog Reset CY7C66013 CY7C66113 level is reached and that CC has risen above approximately 2.5V, and the CC rises above this level minimum) of the last clear. Bit WATCH Execution begins at ...

Page 19

... Interrupt Enable Interrupt Controller Document #: 38-08024 Rev mode 2-bits Q1 Data Out Latch 14 k Q3* Data In Latch Data Interrupt Latch Figure 9-1. Block Diagram of a GPIO Pin CY7C66013 CY7C66113 or Gnd. This also CC Q2 GPIO PIN *Port 0,1,2: Low I sink Port 3: High I sink Page ...

Page 20

... If a ‘1’ is written to the unused data bit and the port is configured with open drain outputs, the unused data bit remains in an indeterminate state. Therefore unused port bit is programmed in open-drain mode, it must be written with a ‘0.’ Notice that the CY7C66013 always requires that P3[7:5] be written with a ‘0.’ When the CY7C66113 is used the P3[7] should be written with a ‘0.’ ...

Page 21

... Hi-Z 0 Output LOW 1 Hi P0.5 Intr P0.4 Intr P0.3 Intr Enable Enable Enable Figure 9-7. Port 0 Interrupt Enable CY7C66013 CY7C66113 Interrupt Polarity 0 Disabled 1 – (Falling Edge) 0 Disabled 1 Disabled 0 Disabled 1 – (Falling Edge) 0 Disabled 1 + (Rising Edge) ADDRESS 0x04 P0.2 Intr P0.1 Intr P0 ...

Page 22

... DAC Port The CY7C66113 features a programmable sink current 8 bit port which is also known as DAC port. Each of these port I/O pins have a programmable current sink. Writing a ‘1’ DAC I/O pin disables the output current sink (I pin HIGH through an integrated 14-k resistor is disabled ...

Page 23

... Enable Bit 5 Enable Bit 4 Enable Bit Figure 10-4. DAC Port Interrupt Enable Enable Bit 5 Enable Bit 4 Enable Bit Figure 10-5. DAC Port Interrupt Polarity CY7C66013 CY7C66113 ADDRESS 0x30 DAC[2] DAC[1] DAC[0] R/W R/W R pull-up pull-up ADDRESS 0x38 –0x3F Isink[2] Isink[1] Isink[0] ...

Page 24

... Figure 11-3. Timer Block Diagram [3] . All bits of this register are cleared on reset LEMPTY DRDY Latch Polarity Polarity Empty R/W R Figure 12-1. HAPI/I C Configuration Register CY7C66013 CY7C66113 Timer Bit 2 Timer Bit Timer Bit 10 Timer Bit 1.024-ms interrupt 128- s interrupt MHz clock To Timer Registers ...

Page 25

... I C Data Data Data 3 R/W R/W R Figure 13- Data Register Figure 13- Status and Control Register CY7C66013 CY7C66113 C-compatible interfaces. HAPI Port Width Position P2[1:0], 0:SCL, 1:SDA P1[1:0], 0:SCL, 1:SDA P2[1:0], 0:SCL, 1:SDA 2 C Status and Control Register 2 C Status and Control 2 C SDA data is connected to bit 1 of GPIO port ...

Page 26

... C-compatible block is busy with a transaction, 0 when transaction is complete. 2 C-compatible block to initiate a master mode transaction by sending a start bit and 2 C-compatible block performs any required arbitration and clock synchronization. IN the 2 C Stop bit is generated. CY7C66013 CY7C66113 2 ARB Received Stop I C Enable Lost/Restart R/W ...

Page 27

... If 1, Data Ready is active HIGH, DReadyPin is active LOW. Determines polarity of Latch Empty bit and LatEmptyPin Latch Empty is active LOW, LatEmptyPin is active HIGH Latch Empty is active HIGH, LatEmptyPin is active LOW. CY7C66013 CY7C66113 2 C start or restart. 2 C-compatible bus, C-compatible pins. When this bit is cleared, ...

Page 28

... WDR can be clearly identified upstream bus reset is received before firmware examines this register, the Bus Reset bit may also be set. Document #: 38-08024 Rev USB Bus Reset Power-On Suspend Interrupt Reset R/W R/W R CY7C66013 CY7C66113 ADDRESS 0xFF Interrupt Reserved Run Enable Sense R R/W R minimum) WATCH Page ...

Page 29

... Enable Interrupt Enable R Figure 16-1. Global Interrupt Enable Register Reserved EPB1 Interrupt EPB0 Interrupt Enable Enable - R/W R CY7C66013 CY7C66113 ADDRESS 0X20 1.024-ms 128- s USB Bus RST Interrupt Interrupt Interrupt Enable Enable Enable R/W R/W R ADDRESS 0X21 EPA2 Interrupt EPA1 Interrupt ...

Page 30

... Bit AddrB EP1 CLR AddrB EP1 IRQ CLR Hub CLR Hub IRQ Interrupt DAC CLR DAC IRQ Acknowledge GPIO CLR GPIO IRQ CLR IRQ Interrupt Priority Encoder CY7C66013 CY7C66113 IRQ Sense IRQ Int Enable Sense Controlled by DI, EI, and RETI Instructions Page ...

Page 31

... USB Address A Endpoint 0 interrupt 0x000A USB Address A Endpoint 1 interrupt 0x000C USB Address A Endpoint 2 interrupt 0x000E USB Address B Endpoint 0 interrupt 0x0010 USB Address B Endpoint 1 interrupt 0x0012 USB Hub interrupt 0x0014 DAC interrupt 0x0016 GPIO interrupt 2 0x0018 I C interrupt CY7C66013 CY7C66113 Function Page ...

Page 32

... Section 14.0. Document #: 38-08024 Rev. *A Port OR Gate (1 input per GPIO pin) 1 Global 1 = Enable GPIO Interrupt 0 = Disable Enable (Bit 5, Register 0x20) Figure 16-4. GPIO Interrupt Structure CY7C66013 CY7C66113 GPIO Interrupt Flip Flop Interrupt D Q Priority Encoder CLR IRQout Interrupt Vector Page ...

Page 33

... C-compatible bus to signal the need for firmware interaction. This generally 2 2 C-compatible bus and leave the I C-compatible hardware in the idle state. 2 C-compatible bus to generate the interrupt interrupt occurs. CY7C66013 CY7C66113 2 C registers. Refer 2 C register contents may be must be placed in series ext Page ...

Page 34

... These features are mapped onto a hub repeater and a hub controller. The hub controller is supported by the processor integrated into the CY7C66013 and CY7C66113 microcontrollers. The hardware in the hub repeater detects whether a USB device is connected to a downstream port and the interface speed of the downstream device. The connection to a downstream port is through a differential signal pair (D+ and D– ...

Page 35

... R/W R/W R Figure 18-2. Hub Ports Speed Port 6 Enable Port 5 Enable Port 4 Enable R/W R/W R Figure 18-3. Hub Ports Enable Register CY7C66013 CY7C66113 ADDRESS 0x4A Port 3 Speed Port 2 Speed Port 1 Speed R/W R/W R ADDRESS 0x49 Port 3 Enable Port 2 Enable Port 1 Enable ...

Page 36

... Figure 18-6. Hub Ports Force Low Register Port 6 Port 5 Port 4 SE0 Status SE0 Status SE0 Status Figure 18-7. Hub Ports SE0 Status Register CY7C66013 CY7C66113 ADDRESS 0x4B Port 2 Port 1 Port 1 Control Bit 0 Control Bit 1 Control Bit 0 R/W R/W R ADDRESS 0x51 2 1 ...

Page 37

... Selective Selective Suspend Suspend Suspend R/W R/W R Figure 18-9. Hub Ports Suspend Register Resume 6 Resume 5 Resume Figure 18-10. Hub Ports Resume Status Register CY7C66013 CY7C66113 ADDRESS 0x50 ADDRESS 0x4D Port 3 Port 2 Port 1 Selective Selective Selective Suspend Suspend Suspend R/W R/W R/W ...

Page 38

... For normal USB operation, all of these bits must be cleared. Table 18-2 shows how the control bits affect the upstream port. Document #: 38-08024 Rev D– Upstream Bus Activity Figure 18-11. USB Status and Control Register CY7C66013 CY7C66113 ADDRESS 0x1F Control Action Control Action Control Action Bit 2 Bit 1 Bit 0 R/W R/W R/W 0 ...

Page 39

... Table 19-1. Endpoint FIFOs are part of user RAM (as shown in Section 5.4.1). Document #: 38-08024 Rev. *A Control Action Device Device Device Address Address Address Bit 5 Bit 4 Bit 3 R/W R/W R Figure 19-1. USB Device Address Registers CY7C66013 CY7C66113 ADDRESSES 0x10(A) and 0x40( Device Device Device Address Address Address Bit 2 Bit 1 Bit 0 R/W R/W R Page ...

Page 40

... EPA2 0xC0 32 EPA1 0xE0 32 EPA0 5 4 Endpoint 0 ACK OUT Received R/W R Figure 19-2. USB Device Endpoint Zero Mode Registers CY7C66013 CY7C66113 [0,1] [1,1] One USB Address Endpoints) Start Start Address Size Label Address 0xD8 8 EPA3 0xA8 0xE0 8 EPA4 0xB0 0xE8 8 ...

Page 41

... Figure 19-3. USB Non-Control Device Endpoint Mode Registers Byte Count Bit Byte Count Bit Byte Count Bit R/W R/W R Figure 19-4. USB Endpoint Counter Registers CY7C66013 CY7C66113 ADDRESSES 0x14, 0x16, 0x44 Mode Bit 2 Mode Bit 1 Mode Bit 0 R/W R/W R ADDRESSES 0x11, 0x13, 0x15, 0x41, 0x43 2 1 ...

Page 42

... For details on what conditions are required to generate an endpoint interrupt, refer to Table 20-2. 4. The contents of the updated endpoint 0 mode and counter registers are locked, except the SETUP bit of the endpoint 0 mode register which was locked earlier. Document #: 38-08024 Rev. *A CY7C66013 CY7C66113 Page ...

Page 43

... Host To Device Data 1/0 Data Packet SETUP Host To Device Data 1/0 Data Packet Figure 19-5. Token/Data Packet Flow Diagram CY7C66013 CY7C66113 Host To Device Hand Shake Packet UPDATE Device To Host ACK NAK STAL 16 C Hand Shake UPDATE Packet UPDATE only if FIFO is written Page ...

Page 44

... On issuance of an ACK this mode is changed by SIE to 1100 (NAK In) count ignore stall check Is set by SIE on an ACK from mode 1111 (Ack In – Status Out) check On issuance of an ACK this mode is changed by SIE to 1110 (NAK In Count – Status Out) CY7C66013 CY7C66113 Comments Page ...

Page 45

... Setup Byte Count (bits 0..5, Figure 17-4) Data Valid (bit 6, Figure 17-4) Data0/1 (bit7 Figure 17-4) PID Status Bits (Bit[7..5], Figure The validity of the received data 17-2) CY7C66013 CY7C66113 In Out ACK Response SIE’s Response to the Host Endpoint Mode bits Changed by the SIE ...

Page 46

... invalid valid invalid CONTROL READ Changes made by SIE to Internal Registers and Mode Bits CY7C66013 CY7C66113 ACK NoChange ignore NoChange ignore NoChange ignore NoChange NAK NoChange NAK NoChange ignore NoChange ignore NoChange Stall NoChange Stall ACK NoChange ignore NoChange ignore NoChange NoChange NAK ...

Page 47

... UC UC invalid ENDPOINT Changes made by SIE to Internal Registers and Mode Bits dval DTOG DVAL COUNT Setup In Out ACK Mode Bits Response Intr CY7C66013 CY7C66113 NoChange ACK Stall Stall NoChange ignore NoChange ignore ACK (back) yes NoChange ACK Stall Stall NoChange ignore ...

Page 48

... Bit 0 Bit 1 Reserve Reserve Reserve Reserve Device Device Device Device Address Address Address Address Bit 6 Bit 5 Bit 4 Bit 3 CY7C66013 CY7C66113 (STALL NoChange stall (STALL ACK (back) yes NoChange ignore NoChange NAK NoChange ignore NoChange TX Read/Write [ Bit 2 Bit 1 Bit 0 /Both P0.2 P0.1 P0 ...

Page 49

... Receive d d Data Byte Byte Byte Valid Count Count Count Bit 5 Bit 4 Bit ACK Mode Bit 3 CY7C66013 CY7C66113 Read/Write [ Bit 2 Bit 1 Bit 0 /Both Byte Byte Byte bbbbbbbb 000000 Count Count Count Bit 2 Bit 1 Bit 0 Mode Bit Mode Bit Mode Bit bbbbbbbb 000000 ...

Page 50

... D+[2] Reserve Force Force Force d Low Low Low D+[7] D–[7] D+[6] WDR USB Bus Power-o Suspend Interrupt Reset n Reset Interrupt CY7C66013 CY7C66113 Read/Write [ Bit 2 Bit 1 Bit 0 /Both Port 3 Port 2 Port 1 bbbbbbbb 000000 Connect Connect Connect Status Status Status Port 3 Port 2 Port 1 ...

Page 51

... Vref OUT 2.2 uF . 22x8(R ext D0- D1- D0+ D1+ D2- XTALO D2+ D3- XTALI D3+ GND GND D4- Vpp D4+ 15K(x8 UDN POWER MANAGEMENT Figure 22-1. Sample Schematic CY7C66013 CY7C66113 ) Page USB-A Vbus D- D+ GND USB-A Vbus D- D+ GND USB-A Vbus D- D+ GND USB-A Vbus D- D+ GND ...

Page 52

... In series with each USB pin 1.5 k ±5 Linear ramp ±5% to Gnd 1.5 k ± REF Including R Resistor ext All ports, LOW to HIGH edge All ports, HIGH to LOW edge is below approximately 2.5V. CC CY7C66013 CY7C66113 = 4.0V to 5.25V) CC Min. Max. 3.15 3.45 –0.4 0 0.2 0.8 2 ...

Page 53

... V = 2.0V DC out V = 2.0V DC out [10 2.0V DC out [11 2.0V out V = 2.0V DC out [12] DAC Port (f = 6.0 MHz) OSC Description / [14, 15] [15] [14, 15] [15] [15] [14, 15] CY7C66013 CY7C66113 = 4.0V to 5.25V) (continued) CC Min. Max. Unit 0.4 V 2.0 V 2.4 V 8.0 24.0 k 0.1 0.3 mA 0.5 1.5 mA 1.6 4 1.6 4.8 mA 0.6 LSB Min ...

Page 54

... Internal Write Internal Addr Figure 25-3. HAPI Read by External Interface from USB Microcontroller Document #: 38-08024 Rev CYC Figure 25-1. Clock Timing t r 90% 90% 10% Figure 25-2. USB Data Signal Timing t OED t OEDR (Ready) Port0 CY7C66013 CY7C66113 t r 10% Int t RD D[23:0] t OEZ Page ...

Page 55

... LEmptyPin (P2.2, output) (Shown for LEMPTY Polarity=0) Internal Read Internal Addr Figure 25-4. HAPI Write by External Device to USB Microcontroller 26.0 Ordering Information Ordering Code PROM Size CY7C66013-PVC 8 KB CY7C66013- CY7C66113-PVC 8 KB Document #: 38-08024 Rev D[23:0] t DSTB t STBLE (not empty) Package Name Package Type ...

Page 56

... Package Diagrams Document #: 38-08024 Rev. *A 48-pin Shrunk Small Outline Package O48 56-pin Shrunk Small Outline Package O56 CY7C66013 CY7C66113 51-85061-*C 51-85062-*C Page ...

Page 57

... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 48-pin (600-Mil) Molded DIP P25 2 C system, provided that the system conforms to the I CY7C66013 CY7C66113 51-85020-* Standard Specification Page ...

Page 58

... Document History Page Document Title: CY7C66013, CY7C66113 Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub Document Number: 38-08024 Issue REV. ECN NO. Date ** 114525 3/27/02 *A 124768 03/20/03 Document #: 38-08024 Rev. *A Orig. of Change DSG Change from Spec number: 38-00591 to 38-08024 MON Added register bit definitions. ...

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