CY7C63001A-PXC Cypress Semiconductor Corp, CY7C63001A-PXC Datasheet - Page 11

• Manufacturer Part Number: CY7C63001A-PXC
• Description: IC MCU 4K USB MCU LS 20-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63001A-PXC

• Applications: USB Microcontroller
• Core Processor: M8A
• Program Memory Type: OTP (4 kB)
• Controller Series: CY7C630xx
• Ram Size: 128 x 8
• Interface: USB
• Number Of I /o: 12
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1616

When servicing an interrupt, the hardware first disables all
interrupts by clearing the Global Interrupt Enable Register.
Next, the interrupt latch of the current interrupt is cleared. This
is followed by a CALL instruction to the ROM address
associated with the interrupt being serviced (i.e., the interrupt
vector). The instruction in the interrupt table is typically a JMP
instruction to the address of the Interrupt Service Routine
(ISR). The user can re-enable interrupts in the interrupt service
routine by writing to the appropriate bits in the Global Interrupt
Enable Register. Interrupts can be nested to a level limited
only by the available stack space.
The Program Counter (PC) value and the Carry and Zero flags
(CF, ZF) are automatically stored onto the Program Stack by
the CALL instruction as part of the interrupt acknowledge
Table 6-3. Interrupt Vector Assignments
6.8.1
Interrupt latency can be calculated from the following
equation:
Interrupt Latency = (Number of clock cycles remaining in the
Document #: 38-08026 Rev. *A
Interrupt Latency
Acknowledge
Interrupt Priority
Interrupt
Interrupt
Register
Enable
Global
0 (Highest)
7 (Lowest)
CLR
1
2
3
4
5
6
current instruction) + (10 clock cycles for
the CALL instruction) + (5 clock cycles
for the JMP instruction)
Enable [7:0]
Interrupt
Interrupt
Logic 1
128-ms
GPIO
Logic 1
Logic 1
CEXT
Figure 6-16. Interrupt Controller Logic Block Diagram
D
D
D
CLK
CLK
CLK
CLR
CLR
CLR
Q
Q
Q
Enable [1]
Enable [6]
Enable [7]
ROM Address
0x0A
0x0C
0x0E
0x00
0x02
0x04
0x06
0x08
process. The user firmware is responsible for ensuring that the
processor state is preserved and restored during an interrupt.
For example the PUSH A instruction should be used as the
first command in the ISR to save the accumulator value. And,
the IPRET instruction should be used to exit the ISR with the
accumulator value restored and interrupts enabled. The PC,
CF, and ZF are restored when the IPRET or RET instructions
are executed.
The Interrupt Vectors supported by the USB Controller are
listed in Table 6-3. Interrupt Vector 0 (Reset) has the highest
priority, Interrupt Vector 7 has the lowest priority. Because the
JMP instruction is two bytes long, the interrupt vectors occupy
two bytes.
For example, if a 5-clock-cycle instruction such as JC is being
executed when an interrupt occurs, the first instruction of the
Interrupt Service Routine executes a minimum of 16 clock
cycles (1+10+5) or a maximum of 20 clock cycles (5+10+5)
after the interrupt is issued. Therefore, the interrupt latency in
this example will be = 20 clock periods = 20 / (12 MHz) = 1.667
last clock cycle in the current instruction.
s. The interrupt latches are sampled at the rising edge of the
Reset
128- s timer interrupt
1.024-ms timer interrupt
USB endpoint 0 interrupt
USB endpoint 1 interrupt
Reserved
GPIO interrupt
Wake-up interrupt
Wake-up CLR
128-ms CLR
128-ms IRQ
1-ms CLR
1-ms IRQ
End P0 CLR
End P0 IRQ
End P1 CLR
End P1 IRQ
GPIO CLR
GPIO IRQ
Wake-up IRQ
Interrupt
Encoder
Priority
Interrupt
Vector
Function
IRQ
CY7C63001A
CY7C63101A
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