CY7C63001A-PXC Cypress Semiconductor Corp, CY7C63001A-PXC Datasheet - Page 13

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CY7C63001A-PXC

Manufacturer Part Number
CY7C63001A-PXC
Description
IC MCU 4K USB MCU LS 20-DIP
Manufacturer
Cypress Semiconductor Corp
Series
M8™r
Datasheet

Specifications of CY7C63001A-PXC

Applications
USB Microcontroller
Core Processor
M8A
Program Memory Type
OTP (4 kB)
Controller Series
CY7C630xx
Ram Size
128 x 8
Interface
USB
Number Of I /o
12
Voltage - Supply
4 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
428-1616

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6.8.3
A USB Endpoint 0 interrupt is generated after the host has
written data to Endpoint 0 or after the USB Controller has
transmitted a packet from Endpoint 0 and receives an ACK
from the host. An OUT packet from the host which is NAKed
by the USB Controller does not generate an interrupt. This
interrupt is masked by the USB EP0 Interrupt Enable bit (bit 3)
of the Global Interrupt Enable Register.
A USB Endpoint 1 interrupt is generated after the USB
Controller has transmitted a packet from Endpoint 1 and has
received an ACK from the host. This interrupt is masked by the
USB EP1 Interrupt Enable bit (bit 4) of the Global Interrupt
Enable Register.
6.8.4
There are two timer interrupts: the 128- s interrupt and the
1.024-ms interrupt. They are masked by bits 1 and 2 of the
Global Interrupt Enable Register respectively. The user should
disable both timer interrupts before going into the suspend
mode to avoid possible conflicts from timer interrupts occurring
just as suspend mode is entered.
6.8.5
A wake-up interrupt is generated when the Cext pin goes
HIGH. This interrupt is latched in the interrupt controller. It can
be masked by the Wake-up Interrupt Enable bit (bit 7) of the
Global Interrupt Enable Register. This interrupt can be used to
perform periodic checks on attached peripherals when the
USB Controller is placed in the low-power suspend mode. See
the Instant-On Feature section for more details.
Typical enumeration steps:
Document #: 38-08026 Rev. *A
1. The host computer sends a SETUP packet followed by a
2. The USB Controller decodes the request and retrieves its
3. The host computer performs a control read sequence and
4. After receiving the descriptor, the host computer sends a
5. The USB Controller stores the new address in its USB
6. The host sends a request for the Device descriptor using
7. The USB Controller decodes the request and retrieves the
DATA packet to USB address 0 requesting the Device
descriptor.
Device descriptor from the program memory space.
the USB Controller responds by sending the Device
descriptor over the USB bus.
SETUP packet followed by a DATA packet to address 0
assigning a new USB address to the device.
Device Address Register after the no-data control
sequence completes.
the new USB address.
Device descriptor from the program memory.
Reserved
b7
0
USB Interrupt
Timer Interrupt
Wake-Up Interrupt
ADR6
R/W
b6
0
Figure 6-20. USB Device Address Register (USB DA – Address 0x12)
ADR5
R/W
b5
0
ADR4
R/W
b4
0
6.9
The USB engine includes the Serial Interface Engine (SIE)
and the low-speed USB I/O transceivers. The SIE block
performs most of the USB interface functions with only minimal
support from the microcontroller core. Two endpoints are
supported. Endpoint 0 is used to receive and transmit control
(including setup) packets while Endpoint 1 is only used to
transmit data packets.
The USB SIE processes USB bus activity at the transaction
level independently. It does all the NRZI encoding/decoding
and bit stuffing/unstuffing. It also determines token type,
checks address and endpoint values, generates and checks
CRC values, and controls the flow of data bytes between the
bus and the Endpoint FIFOs. NOTE: the SIE stalls the CPU for
three cycles per byte when writing data to the endpoint FIFOs
(or 3 * 1/12 MHz * 8 bytes = 2 s per 8-byte transfer).
The firmware handles higher level and function-specific tasks.
During control transfers the firmware must interpret device
requests and respond correctly. It also must coordinate
Suspend/Resume, verify and select DATA toggle values, and
perform function specific tasks.
The USB engine and the firmware communicate though the
Endpoint FIFOs, USB Endpoint interrupts, and the USB
registers described in the sections below.
6.9.1
The USB Controller provides a USB Device Address Register
at I/O location 0x12. Reading and writing this register is
achieved via the IORD and IOWR instructions. The register
contents are cleared during a reset, setting the USB address
of the USB Controller to 0. Figure 6-20 shows the format of the
USB Address Register.
10.The USB Controller retrieves the descriptors from its
11.Enumeration is complete after the host has received all the
8. The host performs a control read sequence and the USB
9. The host generates control reads to the USB Controller to
ADR3
Controller responds by sending its Device descriptor over
the USB bus.
request the Configuration and Report descriptors.
program space and returns the data to the host over the
USB.
descriptors.
R/W
b3
0
USB Engine
USB Enumeration Process
ADR2
R/W
b2
0
ADR1
R/W
b1
0
CY7C63001A
CY7C63101A
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ADR0
R/W
b0
0

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