CY7C63001A-PXC Cypress Semiconductor Corp, CY7C63001A-PXC Datasheet - Page 15

• Manufacturer Part Number: CY7C63001A-PXC
• Description: IC MCU 4K USB MCU LS 20-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63001A-PXC

• Applications: USB Microcontroller
• Core Processor: M8A
• Program Memory Type: OTP (4 kB)
• Controller Series: CY7C630xx
• Ram Size: 128 x 8
• Interface: USB
• Number Of I /o: 12
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1616

6.9.2.2 Endpoint 0 Transmit
The USB Endpoint 0 TX Register located at I/O address 0x10
controls data transmission from Endpoint 0 (see Figure 6-22).
This is a read/write register. All bits are cleared during reset.
Bits 0 to 3 indicate the numbers of data bytes to be transmitted
during an IN packet, valid values are 0 to 8 inclusive. Bit 4
indicates that a received DATA packet error (CRC, PID, or
bitstuffing error) occurred during a SETUP or OUT data phase.
Setting the Stall bit (bit 5) stalls IN and OUT packets. This bit
is cleared whenever a SETUP packet is received by
Endpoint 0. Bit 6 (Data 1/0) must be set to 0 or 1 to select the
DATA packet’s toggle state (0 for DATA0, 1 for DATA1).
After the transmit data has been loaded into the FIFO, bit 6
should be set according to the data toggle state and bit 7 set
to “1”. This enables the USB Controller to respond to an IN
packet. Bit 7 is cleared and an Endpoint 0 interrupt is
generated by the SIE once the host acknowledges the data
transmission. Bit 7 is also cleared when a SETUP token is
Bits 0 to 3 indicate the numbers of data bytes to be transmitted
during an IN packet, valid values are 0 to 8 inclusive.
Bit 4 must be set before Endpoint 1 can be used. If this bit is
cleared, the USB Controller ignores all traffic to Endpoint 1.
Setting the Stall bit (bit 5) stalls IN and OUT packets until this
bit is cleared.
Bit 6 (Data 1/0) must be set to either 0 or 1 depending on the
data packet’s toggle state, 0 for DATA0, 1 for DATA1.
After the transmit data has been loaded into the FIFO, bit 6
should be set according to the data toggle state and bit 7 set
Bit 0 is set by the SIE if any USB activity except idle (D+ LOW,
D– HIGH) is detected. The user program should check and
clear this bit periodically to detect any loss of bus activity.
Writing a 0 to this bit clears it. Writing a 1 does not change its
value.
Bit 1 is used to force the on-chip USB transmitter to the K state
which sends a Resume signal to the host. Bit 2 is used to force
the transmitter to the J state. This bit should normally be set to
Document #: 38-08026 Rev. *A
Reserved
INEN
INEN
R/W
R/W
b7
b7
b7
0
0
0
Reserved
DATA1/0
DATA1/0
R/W
R/W
b6
b6
b6
0
0
0
Figure 6-24. USB Status and Control Register (USB SCR – Address 0x13)
Figure 6-22. USB Endpoint 0 TX Configuration Register (Address 0x10)
Figure 6-23. USB Endpoint 1 TX Configuration Register (Address 0x11)
Reserved
STALL
STALL
R/W
R/W
b5
b5
b5
0
0
0
ENOUTS
EP1EN
ERR
R/W
R/W
R/W
b4
b4
b4
0
0
0
received. The Interrupt Service Routine can check bit 7 to
confirm that the data transfer was successful.
6.9.3
Endpoint 1 is capable of transmit only. The data to be trans-
mitted is stored in the 8-byte Endpoint 1 FIFO located at data
memory space 0x78 to 0x7F.
6.9.3.1 Endpoint 1 Transmit
Transmission is controlled by the USB Endpoint 1 TX Register
located at I/O address 0x11 (see Figure 6-23). This is a
read/write register. All bits are cleared during reset.
to “1”. This enables the USB Controller to respond to an IN
packet. Bit 7 is cleared and an Endpoint 1 interrupt is
generated by the SIE once the host acknowledges the data
transmission.
6.9.4
USB status and control is regulated by USB Status and Control
Register located at I/O address 0x13 as shown in Figure 6-24.
This is a read/write register. All reserved bits must be written
to zero. All bits in the register are cleared during reset.
STATOUTS
zero. However, for resume signaling, force a J state for one
instruction before forcing resume.
Bit 3 is used to automatically respond to the Status stage OUT
of a control read transfer on Endpoint 0. A valid Status stage
OUT contains a DATA1 packet with 0 bytes of data. If the Statu-
sOuts bit is set, the USB engine responds to a valid Status
stage OUT with an ACK, and any other OUT with a STALL.
COUNT3
COUNT3
R/W
R/W
R/W
b3
b3
b3
0
0
0
Endpoint 1
USB Status and Control
COUNT2
COUNT2
FORCEJ
R/W
R/W
b2
b2
b2
0
0
0
COUNT1
COUNT1
FORCEK
R/W
R/W
R/W
b1
b1
b1
0
0
0
CY7C63001A
CY7C63101A
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COUNT0
COUNT0
BUSACT
R/W
R/W
R/W
b0
b0
b0
0
0
0