CY7C63001A-PXC Cypress Semiconductor Corp, CY7C63001A-PXC Datasheet - Page 8

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CY7C63001A-PXC

Manufacturer Part Number
CY7C63001A-PXC
Description
IC MCU 4K USB MCU LS 20-DIP
Manufacturer
Cypress Semiconductor Corp
Series
M8™r
Datasheet

Specifications of CY7C63001A-PXC

Applications
USB Microcontroller
Core Processor
M8A
Program Memory Type
OTP (4 kB)
Controller Series
CY7C630xx
Ram Size
128 x 8
Interface
USB
Number Of I /o
12
Voltage - Supply
4 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
428-1616

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6.5
The USB Controller is equipped with a free-running timer
driven by a clock one-sixth the resonator frequency. Bits 0
through 7 of the counter are readable from the read-only Timer
Register located at I/O address 0x23. The Timer Register is
cleared during a Power-On Reset and whenever Suspend
6.6
Interface with peripherals is conducted via as many as 16
GPIO signals. These signals are divided into two ports: Port 0
and Port 1. Port 0 contains eight lines (P0.0–P0.7) and Port 1
contains up to eight lines (P1.0–P1.7). The number of external
I/O pins depends on the package type. Both ports can be
accessed by the IORD, IOWR, and IOWX instructions. The
Document #: 38-08026 Rev. *A
P1.7
R/W
P0.7
R/W
b7
T.7
b7
b7
1
R
0
1
On-Chip Timer
General Purpose I/O Ports
9
8
P1.6
R/W
P0.6
R/W
b6
T.6
b6
b6
R
1
0
1
7
6
P1.5
R/W
P0.5
R/W
T.5
Figure 6-9. Port 1 Data Register (Address 0x01)
b5
b5
Figure 6-8. Port 0 Data Register (Address 0x00)
b5
R
1
0
1
Figure 6-6. Timer Register (Address 0x23)
5
Figure 6-7. Timer Block Diagram
4
P1.4
R/W
P0.4
R/W
T.4
b4
b4
b4
R
1
0
1
3
mode is entered. Figure 6-6 illustrates the format of this
register and Figure 6-7 is its block diagram.
With a 6 MHz resonator, the timer resolution is 1 s.
The timer generates two interrupts: the 128- s interrupt and
the 1.024-ms interrupt.
Port 0 data register is located at I/O address 0x00 while the
Port 1 data register is located at I/O address 0x01. The
contents of both registers are set HIGH during a reset. Refer
to Figures 6-8 and 6-9 for the formats of the data registers. In
addition to supporting general input/output functions, each I/O
line can trigger an interrupt to the microcontroller. Please refer
to the interrupt section for more details.
2
P1.3
R/W
P0.3
R/W
T.3
b3
b3
b3
R
0
1
1
1
0
P1.2
R/W
P0.2
R/W
T.2
b2
b2
b2
R
0
1
1
8
1.024-ms interrupt
128-
To Timer Register
Resonator Clock/6
P1.1
P0.1
R/W
R/W
T.1
b1
b1
R
b1
0
1
m
1
CY7C63001A
CY7C63101A
s interrupt
Page 8 of 25
P1.0
P0.0
R/W
R/W
T.0
b0
b0
R
b0
0
1
1

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