CY7C63001A-PXC Cypress Semiconductor Corp, CY7C63001A-PXC Datasheet - Page 9

• Manufacturer Part Number: CY7C63001A-PXC
• Description: IC MCU 4K USB MCU LS 20-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63001A-PXC

• Applications: USB Microcontroller
• Core Processor: M8A
• Program Memory Type: OTP (4 kB)
• Controller Series: CY7C630xx
• Ram Size: 128 x 8
• Interface: USB
• Number Of I /o: 12
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1616

Each GPIO line includes an internal R
provides both the pull-up function and slew control. Two
factors govern the enabling and disabling of each resistor: the
state of its associated Port Pull-up register bit and the state of
the Data Register bit. NOTE: The control bits in the Port Pull-
up register are active LOW.
A GPIO line is HIGH when a “1” is written to the Data Register
and a “0” is written to the respective Port Pull-up register.
Writing a “0” to the port Data Register disables the port’s Pull-
up resistor and outputs a LOW on the GPIO line regardless of
the setting in the Port Pull-up Register. The output goes to a
high-Z state if the Data Register bit and the Port Pull-up
Register bit are both “1”. Figure 6-10 illustrates the block
Table 6-2. Output Control Truth Table
To configure a GPIO pin as an input, a “1” should be written to
the Port Data Register bit associated with that pin to disable
the pull-down function of the Isink DAC (see Figure 6-
10).When the Port Data Register is read, the bit value is a “1”
if the voltage on the pin is greater than the Schmitt trigger
threshold, or “0” if it is below the threshold. In applications
where an internal pull-up is required, the R
can be engaged by writing a “0” to the appropriate bit in the
Port Pull-up Register.
Document #: 38-08026 Rev. *A
PULL0.7
b7
W
0
Data Register
0
0
1
1
PULL0.6
Port Pull-Up
Port Isink
Port Data
Register
Suspend
Register
Register
Data Bus
b6
W
0
Bit
PULL0.5
Port Pull-up Register
Figure 6-11. Port 0 Pull-up Register (Address 0x08)
up
b5
W
0
resistor. This resistor
Figure 6-10. Block Diagram of an I/O Line
up
pull-up resistor
0
1
0
1
PULL0.4
b4
W
0
Disable
Isink
DAC
diagram of one I/O line. The Port Isink Register is used to
control the output current level and it is described later in this
section. NOTE: The Isink logic block is turned off during
suspend mode (please refer to the Instant-on Feature section
for more details). Therefore, to prevent higher I
during USB suspend mode, firmware must set ALL Port 0 and
Port 1 Data Register bits (which are not externally driven to a
known state), including those that are not bonded out on a
particular package, to “1” and all Port 0 and Port 1 Pull-Up
Register data bits to “0” to enable port pull-ups before setting
the Suspend bit (bit 3 of the Status and Control Register).
Table 6-2 is the Output Control truth table.
Both Port 0 and Port 1 Pull-up Registers are write only (see
Figures 6-11 and 6-12). The Port 0 Pull-up Register is located
at I/O address 0x08 and Port 1 Pull-up Register is mapped to
address 0x09. The contents of the Port Pull-up Registers are
cleared during reset, allowing the outputs to be controlled by
the state of the Data Registers. The Port Pull-up Registers also
select the polarity of transition that generates a GPIO interrupt.
A “0” selects a HIGH to LOW transition while a “1” selects a
LOW to HIGH transition.
PULL0.3
Pull-up Resistor (‘1’)
Schmitt
Trigger
Output at I/O Pin
b3
W
Sink Current (‘0’)
Sink Current (‘0’)
0
Hi-Z
V
PULL0.2
CC
b2
W
0
R
up
GPIO
Pin
PULL0.1
Interrupt Polarity
b1
W
0
CY7C63001A
CY7C63101A
High to Low
Low to High
High to Low
Low to High
Page 9 of 25
CC
PULL0.0
b0
W
currents
0