CY7C63001C-SXCT Cypress Semiconductor Corp, CY7C63001C-SXCT Datasheet
CY7C63001C-SXCT
Specifications of CY7C63001C-SXCT
Related parts for CY7C63001C-SXCT
CY7C63001C-SXCT Summary of contents
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... SOIC, and 24-pin QSOP packages • Industry standard programmer support R/C EXT RAM NOW™ 128-Byte Timer USB PORT 0 Engine D+,D– P0.0–P0 • 198 Champion Court • San Jose CY7C63001C CY7C63101C 8-bit PORT 1 P1.0–P1 95134-1709 • 408-943-2600 Revised November 28, 2005 ...
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... CY7C63001C has twelve GPIOs and the CY7C63101C has sixteen GPIOs. Notice that each part has eight ‘low-current’ ports (Port 0) with the remaining ports (Port 1) being ‘high-current’ ports. The 12-GPIO CY7C63001C is available in 20-pin PDIP (-PXC) and 20-pin CY7C63101C is available in 24-pin QSOP (-QXC) package. ...
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... P0.0–P0.7 are the 8 I/O lines in Port 0. P1.0–P1.7 are the 8 I/O lines in Port 1. P1.0–P1.3 are P1.0–P1.7 supported in the CY7C63001C. All I/O pins include bit-programmable pull-up resistors. However, the sink current of each pin can be programmed to one of sixteen levels. Besides functioning as GPIO lines, each pin can be programmed as an interrupt input. The interrupt is edge-triggered, with programmable polarity. D+, D– ...
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... Interrupt Vector - 128 µs 0x0002 0x0004 Interrupt Vector - 1.024 ms 0x0006 Interrupt Vector - USB Endpoint 0 0x0008 Interrupt Vector - USB Endpoint 1 0x000A Reserved 0x000C Interrupt Vector - GPIO 0x000E Interrupt Vector - Cext 0x0010 On-chip program Memory 0x0FFF 4K ROM Figure 6-1. Program Memory Space CY7C63001C CY7C63101C Page ...
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... Refer to the Reset section for more information about DSP remapping after reset. Figure 6-2 illustrates the Data Memory Space. Address 0x00 PSP 0x02 0x04 0x70 0x77 0x78 0x7F Figure 6-2. Data Memory Space CY7C63001C CY7C63101C USB FIFO - Endpoint 0 USB FIFO - Endpoint 1 Page ...
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... Control Register is set. Setting the Suspend bit stops the clock oscillator and the interrupt timers and powers down the microcontroller. The detection of any USB activity, the occur- rence of a GPIO Interrupt, or the occurrence of the Cext Interrupt terminates the suspend condition. CY7C63001C CY7C63101C Function Page 9 ...
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... By changing the values of the external resistor and capacitor, the user can fine tune the charge rate of the R-C timing circuit. The format of the Cext register is shown in 8.192 ms No write to WDT register, so WDR goes HIGH Figure 1. Watch Dog Reset (WDR) CY7C63001C CY7C63101C b2 b1 Reserved Reserved 0 0 Instant-on Feature (Suspend Mode) with an external resistor. A “ ...
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... With a 6 MHz resonator, the timer resolution is 1 µs. The timer generates two interrupts: the 128-µs interrupt and the 1.024-ms interrupt T.5 T.4 T Figure 6-5. Timer Register (Address 0x23 Figure 6-6. Timer Block Diagram CY7C63001C CY7C63101C b2 b1 Reserved Reserved T.2 T 1.024-ms interrupt µ 128- s interrupt 1 0 ...
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... Figure 6-7. Port 0 Data Register (Address 0x00 P1.5 P1.4 P1.3 R/W R/W R Figure 6-8. Port 1 Data Register (Address 0x01) Isink DAC Disable Schmitt Trigger Figure 6-9. Block Diagram of an I/O Line CY7C63001C CY7C63101C currents P0.2 P0.1 P0.0 R/W R/W R P1.2 P1.1 P1 ...
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... Figure 6-10. Port 0 Pull-up Register (Address 0x08 PULL1.4 PULL1 Figure 6-11. Port 1 Pull-up Register (Address 0x09 UNUSED ISINK3 Figure 6-12. Port Isink Register for One GPIO Line CY7C63001C CY7C63101C Interrupt Polarity High to Low Low to High High to Low Hi-Z Low to High b2 b1 PULL0.2 PULL0 PULL1.2 PULL1 ...
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... EP0IE R/W R CLR D Q Enable [1] s CLK CLR D Q Enable [6] CLK CLR D Q Enable [7] CLK Figure 3. Interrupt Controller Logic Block Diagram CY7C63001C CY7C63101C XTALOUT XTALIN 1024IE 128IE R/W R µ 128- s CLR µ 128- s IRQ 1-ms CLR 1-ms IRQ IRQ End P0 CLR ...
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... IE0.5 IE0.4 IE0 IE1.5 IE1.4 IE1 CY7C63001C CY7C63101C GPIO Interrupt by on-chip hardware during GPIO interrupt Function Reset 128-µs timer interrupt 1.024-ms timer interrupt USB endpoint 0 interrupt USB endpoint 1 interrupt Reserved GPIO interrupt Wake-up interrupt b2 b1 IE0.2 IE0 IE1.2 IE1 ...
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... It also must coordinate Suspend/Resume, verify and select DATA toggle values, and perform function specific tasks. The USB engine and the firmware communicate though the Endpoint FIFOs, USB Endpoint interrupts, and the USB registers described in the sections below. CY7C63001C CY7C63101C GPIO Interrupt Flip-Flop I D ...
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... The count for DATA following an OUT token is updated if Stall (bit 5 of 0x10 and either EnableOuts or StatusOuts (bits 3 and 4 of 0x13) are 1. The DATA following an OUT is written into the FIFO if EnableOuts is set to 1 and Stall and StatusOuts are COUNT0 TOGGLE R/W R CY7C63001C CY7C63101C ADR2 ADR1 ADR0 R/W R/W R ...
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... No OUT Status No OUT N/Status No OUT Error STALL ERR COUNT3 R/W R/W R STALL EP1EN COUNT3 R/W R/W R CY7C63001C CY7C63101C Endpoint 1 USB Engine Response Toggle Count Update Update Interrupt Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes ...
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... Note: After firmware decodes a SETUP packet and prepares for a subsequent OUT transaction by setting bit 4, bit 4 is not cleared until the hand-shake phase of an ACKed OUT transaction (a NAKed OUT transaction does not clear this bit ENOUTS STATOUTS R/W R CY7C63001C CY7C63101C FORCEJ FORCEK BUSACT R/W R Page ...
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... The single-ended receivers have a switching threshold between 0.8V and 2.0V (TTL inputs). One Bit Time (1.5Mb/s) Signal pins pass output spec levels with minimal reflections and ringing Figure 6-22. Low-speed Driver Signal Waveforms ode Input Voltage (volts) CY7C63001C CY7C63101C Receiver Characteristics Page ...
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... XTALIN XTALOUT 7.5kW 1% 0.1µF 6-MHz Resonator +3.3V Port0 Port0 Switches, Devices, Etc. Port1 Port1 1 D– CEXT CC XTALIN XTALOUT +4.35V (min.) 0.1µF 6-MHz Resonator CY7C63001C CY7C63101C +4.35V (min) 4.7 µF 3.3V Reg 0.1 µF ± kW 4.7 µF Page ...
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... XOR [expr], XOR [X+expr], IOWX [X+expr CPL 1B 6 ASL 1C 4 ASR 1D 5 RLC 1E 13 RRC 1F 4 RET JNC Ax 5 JACC Bx 5 INDEX CY7C63001C CY7C63101C operand opcode cycles 20 4 acc direct 23 7 index 24 8 acc direct 27 7 index 28 8 address 29 5 address 2A 5 ...
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... CC CY7C63001C CY7C63101C = 4.0 to 5.25 volts CC Units Conditions mA µA Resonator off, D– > Voh min mA V µs Ceramic resonator ms ms Linear ramp on V pin [5,6] V 15kΩ ± Gnd ...
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... V 6% 12% V 12% 30% V µA – 0.4 2.0 CY7C63001C CY7C63101C = 4.0 to 5.25 volts CC Conditions [5] Vout = 2.0V DC, Port 0 only [5] Vout = 2.0V DC, Port 0 only [5] Vout = 2.0V DC, Port 1 only [5] Vout = 2.0V DC, Port 1 only [5] Vout = 0.4V DC, Port 1 only [5, 8] Vout = 2.0V DC, Port [9] Port 0 or Port 1 SB [10] Vout = 2 ...
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... Ave. Bit Rate (1.5 Mb/s ± 1.5%) – Next Transition, Figure 9-3 – For Paired Transitions, Figure 9-3 –40 100 ns Figure 9-4 670 ns Accepts as EOP 210 ns µs 1.25 1.50 – next transition, Figure 9-5 –150 150 ns To paired transition, Figure 9-5 CY7C63001C CY7C63101C Conditions [15] [15] [15] [15] Page ...
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... Figure 9-2. USB Data Signal Timing and Voltage Levels T PERIOD Differential Data Lines Document #: 38-08026 Rev CYC Figure 9-1. Clock Timing 90% V crs 10 D− Consecutive Transitions PERIOD JR1 Paired Transitions PERIOD JR2 Figure 9-3. Receiver Jitter Tolerance CY7C63001C CY7C63101C t f 90% 10 JR1 JR2 Page ...
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... Figure 9-4. Differential to EOP Transition Skew and EOP Width T PERIOD Differential Data Lines 10.0 Ordering Information EPROM Ordering Code Size CY7C63001C-PXC 4KB CY7C63001C-SXC 4KB CY7C63001C-SXCT 4KB CY7C63101C-QXC 4KB CY7C63001C-XC 4KB Document #: 38-08026 Rev. *B Crossover Point Extended Crossover Point Diff. Data to SE0 Skew ...
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... Package Diagrams Document #: 38-08026 Rev. *B 20-Lead (300-Mil) Molded DIP P5 24-Lead Quarter Size Outline Q13 CY7C63001C CY7C63101C 51-85011-*A 51-85055-*B Page ...
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... REFERENCE JEDEC MO-119 0.419[10.642] 0.291[7.391] 0.300[7.620] PACKAGE WEIGHT 0.65gms 24 0.026[0.660] 0.032[0.812] SEATING PLANE 0.092[2.336] 0.105[2.667] 0.004[0.101] * 0.004[0.101] 0.0118[0.299] CY7C63001C CY7C63101C MAX. PART # S20.3 STANDARD PKG. SZ20.3 LEAD FREE PKG. 0.0091[0.231] 0.015[0.381] 0.0125[0.317] 0.050[1.270] 51-85024-*B MIN. MAX. PART # S24.3 STANDARD PKG. SZ24.3 LEAD FREE PKG. ...
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... Package Diagrams (continued) Table 11-1 below shows the die pad coordinates for the CY7C63001C-XC. The center location of each bond pad is Table 11-1. CY7C63001C-XC Probe Pad Coordinates in microns ((0,0) to bond pad centers) Pin X Pad # Name (microns) 1 Port00 676.00 2 Port01 507.35 3 Port02 338 ...
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... Document History Page Document Title: CY7C63001C, CY7C63101C Universal Serial Bus Microcontroller Document Number: 38-08026 Issue REV. ECN NO. Date ** 116223 06/12/02 *A 276070 See ECN *B 408068 See ECN Document #: 38-08026 Rev. *B Orig. of Change Description of Change DSG Change from Spec number: 38-00662 to 38-08026 BON Added die form and bond pad information ...