IC MPU RABIT3000A 55.5MHZ128LQFP

20-668-0011

Manufacturer Part Number20-668-0011
DescriptionIC MPU RABIT3000A 55.5MHZ128LQFP
ManufacturerRabbit Semiconductor
20-668-0011 datasheet
 


Specifications of 20-668-0011

Processor TypeRabbit 3000 8-BitSpeed55.5MHz
Voltage2.5V, 2.7V, 3V, 3.3VMounting TypeSurface Mount
Package / Case128-LQFPData Bus Width8 bit
Maximum Clock Frequency55.5 MHzOperating Supply Voltage1.8 V to 3.6 V
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
Minimum Operating Temperature- 55 CNumber Of Programmable I/os56
Lead Free Status / RoHS StatusLead free / RoHS CompliantFeatures-
Other names316-1061  
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Rabbit
3000 Microprocessor
User’s Manual
019-0108_W

20-668-0011 Summary of contents

  • Page 1

    ... Rabbit 3000 Microprocessor User’s Manual 019-0108_W ...

  • Page 2

    ... Rabbit 3000 Microprocessor User’s Manual Part Number 019-0108 ©2002–2010 Digi International Inc. • All rights reserved. Digi International reserves the right to make changes and improvements to its products without providing notice. Trademarks Rabbit and Dynamic C are registered trademarks of Digi International Inc. ...

  • Page 3

    Chapter 1. The Rabbit 3000 Processor 1.1 Introduction...........................................................................................................................................1 1.2 Features .................................................................................................................................................1 1.3 Block Diagram ......................................................................................................................................3 1.4 Basic Specifications ..............................................................................................................................4 1.5 Comparing Rabbit Microprocessors .....................................................................................................5 Chapter 2. Clocks 2.1 Overview...............................................................................................................................................7 2.1.1 Block Diagram .............................................................................................................................8 2.1.2 Registers .......................................................................................................................................8 2.2 Dependencies ........................................................................................................................................9 2.2.1 ...

  • Page 4

    ... Other Registers .......................................................................................................................... 66 8.2.4 Interrupts .................................................................................................................................... 66 8.3 Operation ............................................................................................................................................ 66 8.4 Register Descriptions ......................................................................................................................... 67 Chapter 9. Parallel Port B 9.1 Overview ............................................................................................................................................ 69 9.1.1 Block Diagram ........................................................................................................................... 70 9.1.2 Registers .................................................................................................................................... 70 9.2 Dependencies ..................................................................................................................................... 70 9.2.1 I/O Pins ...................................................................................................................................... 70 9.2.2 Clocks ........................................................................................................................................ 70 9.2.3 Other Registers .......................................................................................................................... 70 9.2.4 Interrupts .................................................................................................................................... 71 9.3 Operation ............................................................................................................................................ 71 9.4 Register Descriptions ......................................................................................................................... 71 Rabbit 3000 Microprocessor User’s Manual ...

  • Page 5

    Chapter 10. Parallel Port C 10.1 Overview...........................................................................................................................................73 10.1.1 Block Diagram .........................................................................................................................74 10.1.2 Registers ...................................................................................................................................74 10.2 Dependencies ....................................................................................................................................74 10.2.1 I/O Pins ....................................................................................................................................74 10.2.2 Clocks .......................................................................................................................................74 10.2.3 Other Registers .........................................................................................................................74 10.2.4 Interrupts ..................................................................................................................................74 10.3 Operation ..........................................................................................................................................75 10.4 Register Descriptions ........................................................................................................................76 Chapter 11. ...

  • Page 6

    ... Other Registers ...................................................................................................................... 116 16.2.4 Interrupts ................................................................................................................................ 116 16.3 Operation ........................................................................................................................................ 117 16.3.1 Handling Interrupts ................................................................................................................ 117 16.3.2 Example ISR .......................................................................................................................... 117 16.4 Register Descriptions ..................................................................................................................... 118 Chapter 17. Serial Ports A – D 17.1 Overview ........................................................................................................................................ 121 17.1.1 Block Diagram ....................................................................................................................... 123 17.1.2 Registers ................................................................................................................................ 124 17.2 Dependencies ................................................................................................................................. 125 17.2.1 I/O Pins .................................................................................................................................. 125 17 ...

  • Page 7

    ... I/O Pins ..................................................................................................................................171 20.2.2 Clocks .....................................................................................................................................171 20.2.3 Other Registers .......................................................................................................................171 20.2.4 Interrupts ................................................................................................................................171 20.3 Operation ........................................................................................................................................172 20.3.1 Input-Capture Channel ...........................................................................................................172 20.3.2 Handling Interrupts ................................................................................................................172 20.3.3 Example ISR ..........................................................................................................................172 20.3.4 Example Applications ............................................................................................................173 20.4 Register Descriptions ......................................................................................................................174 Chapter 21. Quadrature Decoder 21.1 Overview.........................................................................................................................................177 21 ...

  • Page 8

    ... Chapter 25. Low-Power Operation 25.1 Overview ........................................................................................................................................ 201 25.1.1 Registers ................................................................................................................................ 202 25.2 Operation ........................................................................................................................................ 203 25.2.1 Unused Pins ........................................................................................................................... 203 25.2.2 Clock Rates ............................................................................................................................ 203 25.2.3 Short Chip Selects ................................................................................................................. 204 25.2.4 Self-Timed Chip Selects ........................................................................................................ 209 25.3 Register Descriptions ..................................................................................................................... 210 Chapter 26. System/User Mode 26.1 Overview ........................................................................................................................................ 213 26.1.1 Registers ................................................................................................................................ 214 26 ...

  • Page 9

    ... Enabling the System/User Mode ............................................................................................219 26.3.5 System/User Mode Instructions .............................................................................................220 26.3.6 System Mode Violation Interrupt ..........................................................................................221 26.3.7 Handling Interrupts in the System/User Mode ......................................................................222 26.4 Register Descriptions ......................................................................................................................224 Chapter 27. Specifications 27.1 DC Characteristics ..........................................................................................................................231 27.2 AC Characteristics ..........................................................................................................................233 27.3 Memory Access Times ...................................................................................................................234 27 ...

  • Page 10

    ... Rabbit 3000 Microprocessor User’s Manual ...

  • Page 11

    ... Rabbit Semiconductor was formed expressly to design a better microprocessor for use in small- and medium-scale single-board computers. The first microprocessors was the Rabbit 2000. Besides the Rabbit 3000, Rabbit 4000 and Rabbit 5000 microprocessors are also available. Rabbit microprocessor designers have had years of experience using Z80, Z180, and HD64180 microprocessors in small single-board computers ...

  • Page 12

    ... I/O instructions. Hardware-supported breakpoints ease debugging by trapping on code execution or data reads and writes. The Rabbit 3000 requires no external memory driver or interface-logic. Its 20-bit address bus, 8-bit data bus, three chip-select lines, two output-enable lines, and two write-enable lines can be interfaced directly with up to six memory devices ...

  • Page 13

    Block Diagram Figure 1-1. Rabbit 3000 Block Diagram Chapter 1 The Rabbit 3000 Processor 3 ...

  • Page 14

    ... CMOS-compatible Clock speed/8 max. asynchronous 20-bit 8-bit Ten 8-bit and one 10-bit with 2 match registers Yes, battery backable External Yes 1×, 2×, /2, /3, /4, /6, /8 Sleepy (32 kHz) Ultra-Sleepy (16 kHz) 8 data, 8 address lines Rabbit 3000 Microprocessor User’s Manual ...

  • Page 15

    ... Comparing Rabbit Microprocessors The Rabbit 2000, Rabbit 3000, Rabbit 4000, and Rabbit 5000 features are compared below. Feature Maximum Clock Speed, industrial Maximum Clock Speed, commercial Maximum Crystal Frequency Main Oscillator (may be doubled internally up to maximum clock speed) 32.768 kHz Crystal Oscillator ...

  • Page 16

    ... Rabbit 3000 is no longer sold. 6 Rabbit 5000 Rabbit 4000 Yes Yes ( ( ( ( Clock Speed/8 Clock Speed/8 10/100Base-T 10Base channels 2 channels Rabbit 3000 Microprocessor User’s Manual Rabbit 3000 Rabbit 2000 Yes None ( ( (E, F) None 6 None 2 None Clock Speed/8 Clock Speed/32 None None 2 None 2 channels None ...

  • Page 17

    ... Overview The Rabbit 3000 supports two separate clocks—the main clock and the 32 kHz clock. The main clock is used to derive the processor clock and the peripheral clock inside the proces- sor. The 32 kHz clock is used to drive the asynchronous serial bootstrap, the real-time clock, the periodic interrupt, and the watchdog timers ...

  • Page 18

    ... Global Power Save Control Register Global Clock Double Register 8 I/O Mnemonic R/W Address GCSR 0x0000 R/W GCM0R 0x000A W GCM1R 0x000B W GPSCR 0x000D W GCDR 0x000F W Rabbit 3000 Microprocessor User’s Manual Rabbit Rabbit 3000 3000A Reset Reset 11000000 00000000 00000000 0000x000 00000000 00000000 ...

  • Page 19

    Dependencies 2.2.1 I/O Pins The main clock input is on the CLKI pin. There is an internal Schmitt trigger on this pin to remove problems with noise on slowly transitioning signals. The main clock disable output is on the ...

  • Page 20

    ... CLKIEN output signal When the 32 kHz clock is enabled in GCSR, it can be further divided generate even lower frequencies by enabling those modes in bits 0–2 of GPSCR. See Table 2-4 for more details. 10 Table 2-1. Clock Modes Peripheral Clock ...

  • Page 21

    ... Figure 2-1. Effects of Spectrum Spreader There are three settings that correspond to normal and strong spreading in the 0–50 MHz and >50 MHz main clock range. Each setting will affect the clock cycle differently; the maximum cycle shortening (at 1.8 V and 25° ...

  • Page 22

    ... If the doubler is not used, then the spreader affects every clock cycle, and the clock low time is reduced. 12 Strong Spreading Normal Spreading 100 150 200 250 Frequency (MHz) Rabbit 3000 Microprocessor User’s Manual 350 300 ...

  • Page 23

    ... GCDR for various oscillator frequencies. Table 2-3. Recommended Delays Set In GCDR for Clock Doubler Recommended GCDR Value Chapter 2 Clocks Frequency Range 7.3728 MHz 0x000F 0x000B 7.3728–11.0592 MHz 0x0009 11.0592–16.5888 MHz 0x0006 16.5888–20.2752 MHz 0x0003 20.2752–52.8384 MHz 0x0000 >52.8384 MHz 13 ...

  • Page 24

    ... The doubled-clock low time is subject to wide (50%) variation since it depends on process parameters, temperature, and voltage. The times given above are for a core supply voltage of 3.3 V and a temperature of 25°C. The doubled-clock low time increases by 20% when the voltage is reduced to 2.5 V, and increases by about 40% when the voltage is reduced further to 2.0 V. The values increase or decrease by 1% for each 5° ...

  • Page 25

    Memory access time is not affected because the memory bus cycle is 2 clocks long and ...

  • Page 26

    ... The values of resistors and capacitors may need to be adjusted for various frequen- cies and crystal load capacitances. Rabbit’s Technical Note TN235, “External 32.768 kHz Oscillator Circuits,“ is available on the Rabbit Web site and goes into this circuit in detail. Figure 2-4. Basic 32.768 kHz Oscillator Circuit The 32 ...

  • Page 27

    ... The 32 kHz oscillator can be used to drive the processor and peripheral clock to provide significant power savings in “ultra-sleepy” modes. The 32 kHz oscillator can be divided provide clock speeds as low as 2.048 kHz. Special self-timed chip selects are available to keep the memory devices enabled for as short a time as possible when an ultra-sleepy mode is enabled ...

  • Page 28

    ... Description GCSR Clock Select Field Peripheral Main Clock Oscillator osc/8 osc osc osc/2 32 kHz or fraction 32KHz or fraction osc/4 osc/6 Rabbit 3000 Microprocessor User’s Manual (Address = 0x0000) Power-Save CS if Enabled by GPSCR on short CS option on short CS option on none on short CS option self-timed option on ...

  • Page 29

    Global Clock Modulator 0 Register Bit(s) Value 0 Enable normal spectrum spreading Enable strong spectrum spreading. 6:0 These bits are reserved and should be written with zeros. Global Clock Modulator 1 Register Bit(s) Value 0 Disable the spectrum ...

  • Page 30

    ... Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 31

    Global Output Control Register Bit(s) Value 00 CLK pin is driven by perclk. 01 CLK pin is driven by perclk/2. 7:6 10 CLK pin is low. 11 CLK pin is high. 00 STATUS pin is active (low) during a first ...

  • Page 32

    ... Rabbit 3000 Microprocessor User’s Manual ...

  • Page 33

    ... Overview The Rabbit 3000’s /RESET pin initializes everything in the processor except for the real- time clock registers write cycle is in progress, it waits until the write cycle is com- pleted to avoid potential memory corruption. After reset, the Rabbit 3000 checks the state of the SMODE pins. Depending on their ...

  • Page 34

    ... Pulling the /RESET pin low will initialize everything in the Rabbit 3000 except for the real-time clock registers. /CS1 — During reset the impedance of the /CS1 pin is high, and all other memory and I/O control signals are held high. The special behavior of /CS1 allows an external RAM to be powered by the same source as the VBATIO pin (which powers /CS1) ...

  • Page 35

    Operation Pulling the /RESET pin low will initialize everything in the Rabbit 3000 except for the real-time clock registers. The reset of the Rabbit 3000 is delayed until the completion of any write cycles in progress; reset takes effect ...

  • Page 36

    ... If both SMODE pins are zero, the Rabbit 3000 begins fetching instructions from the memory device on /CS0 and /OE0. • If either of the SMODE pins is high, the processor will enter the bootstrap mode and accept triplets from either Serial Port A or the slave port good practice to place pulldown resistors on the SMODE pins to ensure proper operation of your design ...

  • Page 37

    Register Descriptions Slave Port Control Register Bit(s) Value 7 0 Program fetch as a function of the SMODE pins. 1 Ignore the SMODE pins program fetch function. 6:5 Read These bits report the state of the SMODE pins. Write ...

  • Page 38

    ... Rabbit 3000 Microprocessor User’s Manual ...

  • Page 39

    ... Priority 3 secondary watchdog interrupt when it is not reset within that time. The primary use for the secondary watchdog is to act as a safety net for the periodic interrupt — if the secondary watchdog is reloaded in the periodic interrupt, it will count down to zero if the periodic interrupt stops occurring. In addition, it can be used as a periodic interrupt on its own ...

  • Page 40

    ... W SWDTR 0x000C W GOCR 0x000E W GROM 0x002C R GRAM 0x002D R GCPU 0x002E R GREV 0x002F R 0xx00000 Rabbit 3000 Microprocessor User’s Manual Rabbit 3000 3000A Reset Reset 11000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00000000 00000000 — 11111111 00000000 0xx00000 0xx00000 0xx00010 ...

  • Page 41

    ... CLK pin can output the peripheral clock, the peripheral clock divided by two driven high or low; • the STATUS pin can be active low during the first byte of each opcode fetch, active low during an interrupt acknowledge, or driven high or low; • the /WDTOUT pin can be active low whenever the watchdog timer resets the device or driven low ...

  • Page 42

    ... The real-time clock can be reset by writing the sequence 0x0040 – 0x0080 to RTCCR. It can be reset and left in the byte increment mode by writing 0x0040 – 0x00C0 to RTCCR and then writing bytes repeatedly to RTCCR to increment the appropriate bytes of the real-time clock ...

  • Page 43

    ... The secondary watchdog timer is disabled on reset, unless the reset occurs because the primary watchdog timer times out while the secondary watchdog timer is enabled. The BIOS provided by Rabbit Semiconductor in Dynamic C avoids this bug by disabling the secondary watchdog on startup or reset by writing 0x005F to WDTCR. The following steps explain how to use the secondary watchdog timer ...

  • Page 44

    ... Description GCSR Clock Select Field Peripheral Main Clock Oscillator osc/8 osc osc osc/2 32 kHz or fraction 32KHz or fraction osc/4 osc/6 Rabbit 3000 Microprocessor User’s Manual (Address = 0x0000) Power-Save CS if Enabled by GPSCR on short CS option on short CS option on none on short CS option self-timed option on ...

  • Page 45

    ... Resets all six bytes of the RTC counter to 0x0000 and enters byte increment 0x00C0 mode—precede this command with 0x0040 arm command. This bit combination must be used with every byte increment write to increment clock(s) register corresponding to bit(s) set to "1". Example: 01001101 ...

  • Page 46

    ... The timer counts modulo where n is the programmed time constant. The secondary watchdog timer can be disabled by writing the sequence 0x005A – 0x0052 – 0x0044 to this register. 36 (WDTCR) (Address = 0x0008) ...

  • Page 47

    Global Output Control Register Bit(s) Value 00 CLK pin is driven by perclk. 01 CLK pin is driven by perclk/2. 7:6 10 CLK pin is low. 11 CLK pin is high. 00 STATUS pin is active (low) during a first ...

  • Page 48

    ... These bits report the state of the SMODE pins. 4:0 00000 Revision identifier for Rabbit 3000 version of the chip. 00001 Revision identifier for Rabbit 3000A version of the chip. 38 (GCPU) (Address = 0x002E) Description (GREV) (Address = 0x002F) Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 49

    ... The 8-bit mode allows wait states to be specified for each device. The Rabbit 3000’s physical memory space contains four consecutive banks, each of which can be mapped to an individual chip-select/enable strobe pair. The banks can be set for equal sizes ranging from 128 MB, providing a total physical memory range from 512 ...

  • Page 50

    ... XPC register possible to run code in the XPC window, providing an easy means of storing and executing code beyond the 64 KB logical memory space. Special call and return instructions to physical addresses are provided that automatically update the XPC register as necessary. Figure 5-2. Logical and Physical Memory Mapping 40 Rabbit 3000 Microprocessor User’s Manual ...

  • Page 51

    ... The Rabbit 2000 and 3000 have numerous instructions for reading and writing data to logical addresses, but only limited support for reading and writing data to a physical memory address. The 64 KB logical memory space limitation can also be expanded by using the separate instruction and data space mode. When this mode is enabled, address bit A16 is inverted ...

  • Page 52

    ... WPHR 0x0461 W WPSAR 0x0480 W WPSALR 0x0481 W WPSAHR 0x0482 W WPSBR 0x0484 W WPSBLR 0x0485 W WPSBHR 0x0486 W Rabbit 3000 Microprocessor User’s Manual Rabbit Rabbit 3000 3000A Reset Reset 00000000 00000000 00000000 11111111 00001000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxx000 00000000 xxxx0000 00000000 — 00000000 — ...

  • Page 53

    ... There are three chip select pins: /CS0, /CS1, and /CS2; two read strobes, /OE0 and /OE1; and two write strobes, /WE0 and /WE1. There are eight dedicated data bus pins, D0 through D7. There are 20 dedicated address pins, A0 through A19. 5.2.2 Clocks All memory operations are clocked by the processor clock. ...

  • Page 54

    ... KB block boundary. The data and stack segment mappings are set by writing to the appropriate register, as shown in Table 5-1. The DATASEG and STACKSEG registers provide backwards compatibility to the Rabbit 2000 processor. Table 5-1. Memory Management Registers Register DATASEG ...

  • Page 55

    Operation On startup Memory Bank 0 is enabled to use /CS0, /OE0, and /WE0 with four wait states and write protection enabled expected that an external flash device containing startup code be attached to those strobes. ...

  • Page 56

    ... KB of logical memory. Starting with the Rabbit 3000A, the RAM segment register (RAMSR) provides a shortcut for updating code by accessing it as data. It provides a “window” that uses the instruction address decoding when read or written as data. This mapping will only occur when the RAMSR is within the root or data segements ...

  • Page 57

    ... Priority 3 stack violation interrupt occurs. The 16-byte buffer exists to allow stack protec- tion even if the stack is placed against a memory segment boundary. Figure 5-6 shows one possible stack layout. A 2048-byte stack is set up by setting STKHLR to 0x00E0, STKLLR to 0x00D8, and SP to 0xDFF0. Any stack-relative mem- ory accesses above 0xDFEF (i ...

  • Page 58

    ... Bit(s) Value Internal I/O addresses are decoded using only the lower eight bits of the internal * 0 I/O address bus. This restricts internal I/O addresses to the range 0x0000– 7 0x00FF. Internal I/O addresses are decoded using all 15 bits of the address internal I/O 1 address bus. This option must be selected to access internal I/O addresses of 0x0100 and higher ...

  • Page 59

    Data Segment Register Bit(s) Value 7:0 Read The current contents of this register are reported. Eight LSBs (MSBs are set to zero by write) of physical address offset to use if: Write SEGSIZ[3:0]  Addr[15:12] < SEGSIZ[7:4] Segment Size Register ...

  • Page 60

    ... Bit(s) Value 7:1 These bits are reserved and should be written with zeros Write protection in User Mode only. 1 Write protection in System and User modes. 50 (MECR) (Address = 0x0018) Description (MTCR) (Address = 0x0019) Description (WPCR) (Address = 0x0440) Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 61

    Stack Limit Control Register Bit(s) Value 7:1 These bits are reserved and should be written with zeros Disable stack-limit checking. 1 Enable stack-limit checking. Stack Low Limit Register Bit(s) Value Lower limit for stack-limit checking stack ...

  • Page 62

    ... Enable 64Kwrite-protect for relative address 0x30000–0x3FFFF. 0 Disable 64K write-protect for relative address 0x20000–0x2FFFF Enable 64K write-protect for relative address 0x20000–0x2FFFF. 0 Disable 64K write-protect for relative address 0x10000–0x1FFFF Enable 64K write-protect for relative address 0x10000–0x1FFFF. 0 Disable 64K write-protect for relative address 0x00000–0x0FFFF. ...

  • Page 63

    ... Enable 64K write-protect for relative address 0xB0000–0xBFFFF. 0 Disable 64K write-protect for relative address 0xA0000–0xAFFFF Enable 64K write-protect for relative address 0xA0000–0xAFFFF. 0 Disable 64K write-protect for relative address 0x90000–0x9FFFF Enable 64K write-protect for relative address 0x90000–0x9FFFF. 0 Disable 64K write-protect for relative address 0x80000– ...

  • Page 64

    ... Enable 4K write protect for physical address 0x3000–0x3FFF in WP Segment Disable 4K write protect for physical address 0x2000–0x2FFF in WP Segment x. 1 Enable 4K write protect for physical address 0x2000–0x2FFF in WP Segment Disable 4K write protect for physical address 0x1000–0x1FFF in WP Segment x. 1 Enable 4K write protect for physical address 0x1000– ...

  • Page 65

    ... Enable 4K write protect for physical address 0xB000–0xBFFF in WP Segment Disable 4K write protect for physical address 0xA000–0xAFFF in WP Segment x. 1 Enable 4K write protect for physical address 0xA000–0xAFFF in WP Segment Disable 4K write protect for physical address 0x9000–0x9FFF in WP Segment x. 1 Enable 4K write protect for physical address 0x9000– ...

  • Page 66

    ... Rabbit 3000 Microprocessor User’s Manual ...

  • Page 67

    ... Every time an interrupt is handled or an IPSET instruction occurs, the value in the register is shifted left by two bits, and the new priority placed in bits 0–1. When an IPRES or IRET instruction occurs, the value shifted right by two bits (bits 0–1 are shifted into bits 6–7). On reset, the processor starts at Priority 3. ...

  • Page 68

    ... To ensure proper operation, all interrupt handler routines should be written according to the following guidelines. • Push all registers to be used by the routine onto the stack before use, and pop them off the stack before returning from the ISR. • Keep the ISR as short and fast as possible. ...

  • Page 69

    ... Table 6-2 shows the structure of the external interrupt vector table. Each interrupt vector falls on a 16-byte boundary inside the table. Table 6-2. External Interrupt Vector Table Structure Chapter 6 Interrupts Offset 0x0000+ 0x0000 External Interrupt 0 0x0010 External Interrupt 1 0x0020 — 0x0030 — 0x0040 — 0x0050 — 0x0060 — 0x0070 — 59 ...

  • Page 70

    ... There is a priority among interrupts if multiple requests are pending, as shown in Table 6-3. Interrupts marked as “cleared automatically” have their requests cleared when the inter- rupt is first handled. Table 6-3. Interrupt Priorities Priority Interrupt Source Highest External 1 External 0 Periodic (2 kHz) Quadrature Decoder ...

  • Page 71

    Overview The Rabbit 3000 has two external interrupts. Each interrupt has two input pins that can be used to trigger the interrupt. The inputs have a pulse catcher that can detect rising, falling, or both edges. The pulse needs ...

  • Page 72

    ... When an interrupt occurs, read PEDR to determine which pin has a signal if more than one pin is enabled for a given external interrupt. 62 Mnemonic I/O Address I0CR 0x0098 I1CR 0x0099 Register Pins I0CR PE0, PE4 I1CR PE1, PE5 Rabbit 3000 Microprocessor User’s Manual R/W Reset W xx000000 W xx000000 ...

  • Page 73

    ... External interrupt Routine #0 (programmed priority could be 3) int2: PUSH IP ; save interrupt priority IPSET 1 ; set to priority really desired (1, 2, etc.) ; insert body of interrupt routine here ; POP IP ; get back entry priority IPRES ; restore interrupted routine’s priority RET ; return from interrupt Chapter 7 External Interrupts 63 ...

  • Page 74

    ... Parallel Port E low nibble interrupt on both edges. 1:0 00 This external interrupt is disabled. 01 This external interrupt uses Interrupt Priority 1. 10 This external interrupt uses Interrupt Priority 2. 11 This external interrupt uses Interrupt Priority 3. 64 (I0CR) (Address = 0x0098) (I1CR) (Address = 0x0099) Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 75

    Overview Parallel Port byte-wide port that can be used as an input or an output port. Parallel Port A is also used as the data bus for the slave port and external I/O bus. The Slave ...

  • Page 76

    ... Port F has full function Parallel Port A cannot be used as inputs, use any pins on Parallel Port F not used for PWM or serial clock outputs as inputs and take the precau- tion of setting up Parallel Port F before the conflicting functionality of Parallel Port A is enabled. Refer to Rabbit’s Technical Note TN228, Rabbit 3000 Parallel Port F Bug, for more information. 66 Function Used to set up Parallel Port A ...

  • Page 77

    ... Parallel Port A Data Register Bit(s) Value 7:0 Read The current state of Parallel Port A pins PA7–PA0 is reported. The Parallel Port A buffer is written with this value for transfer to the Parallel Write Port A output register on the next rising edge of the peripheral clock. Slave Port Control Register ...

  • Page 78

    ... Rabbit 3000 Microprocessor User’s Manual ...

  • Page 79

    ... Parallel Port byte-wide port with each bit programmable for direction. The Parallel Port B pins are also used to access other peripherals on the chip—the slave port, the exter- nal I/O address bus, and clock I/O for clocked serial mode option for Serial Ports A and B. ...

  • Page 80

    ... Serial Ports A and B. On startup, bits 6 and 7 are outputs set low for backwards compatibility with the Rabbit 2000. All other pins are inputs. Note that when the external I/O bus or slave port is enabled in SPCR, the Parallel Port B pins associated with those peripherals perform those actions, no matter what the settings are in PBDR or PBDDR ...

  • Page 81

    ... Bit(s) Value 7:0 Read The current state of Parallel Port B pins PB7–PB0 is reported. The Parallel Port B buffer is written with this value for transfer to the Parallel Write Port B output register on the next rising edge of the peripheral clock. Parallel Port B Data Direction Register ...

  • Page 82

    ... Slave port interrupts are disabled. (Write 01 Slave port interrupts use Interrupt Priority 1. only) 10 Slave port interrupts use Interrupt Priority 2. 11 Slave port interrupts use Interrupt Priority 3. * Introduced with Rabbit 3000A chip. 72 (SPCR) Description * . Rabbit 3000 Microprocessor User’s Manual (Address = 0x0024) ...

  • Page 83

    ... Parallel Port byte-wide port that has four inputs and four outputs. The even-numbered ports—PC0, PC2, PC4, and PC6—are outputs. The odd-numbered ports—PC1, PC3, PC5, and PC7—are inputs.. These are simple inputs and outputs controlled and reported in the Port C Data Register (PCDR). ...

  • Page 84

    ... I/O Pins Parallel Port C uses pins PC0 through PC7. These pins can be used individually as data inputs or outputs; as serial port transmit and receive for Serial ports A–D. The Input Cap- ture peripheral can also watch pins PC7, PC5, PC3, and PC1. ...

  • Page 85

    Operation When PCDR is read, bits and 7 return the logic level on the pin. Bits and 6 return the value of the signal driving the output buffers. The signal driving the output ...

  • Page 86

    ... Parallel Port C Data Register Bit(s) Value 7:0 Read The current state of Parallel Port C pins PC7–PC0 is reported. The Parallel Port C buffer is written with this value for transfer to the Parallel Write Port C output register on the next rising edge of the peripheral clock. Parallel Port C Function Register ...

  • Page 87

    Serial Port x Control Register Bit(s) Value 7 operation. These bits are ignored in the asynch mode clocked serial mode, start a byte receive operation clocked serial mode, start a byte transmit operation. In ...

  • Page 88

    ... Serial Port D clock is on Parallel Port F pin 0 00 The serial port interrupt is disabled. 01 The serial port uses Interrupt Priority 1. 1:0 10 The serial port uses Interrupt Priority 2. 11 The serial port uses Interrupt Priority 3. 78 (SCCR) (Address = 0x00E4) (SDCR) (Address = 0x00F4) Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 89

    ... PDDR. To alleviate this potential problem, each bit of the port can be written individually using a separate address for each bit. Table 11-1. Parallel Port D Alternate Pin Functions Pin Name Serial Ports A–B PD7 ARXA PD6 — ...

  • Page 90

    ... PDFR 0x0065 PDDCR 0x0066 PDDDR 0x0067 PDB0R 0x0068 PDB1R 0x0069 PDB2R 0x006A PDB3R 0x006B PDB4R 0x006C PDB5R 0x006D PDB6R 0x006E PDB7R 0x006F Rabbit 3000 Microprocessor User’s Manual R/W Reset R/W xxxxxxxx W xx00xx00 W xxxxxxxx W xxxxxxxx W 00000000 W xxxxxxxx W xxxxxxxx W xxxxxxxx W xxxxxxxx W xxxxxxxx ...

  • Page 91

    Dependencies 11.2.1 I/O Pins Parallel Port D uses pins PD0 through PD7. These pins can be used individually as data inputs or outputs, as serial port transmit and receive for Serial Ports A and PWM outputs. ...

  • Page 92

    ... Parallel Port D Data Register Bit(s) Value 7:0 Read The current state of Parallel Port D pins PD7–PD0 is reported. The Parallel Port D buffer is written with this value for transfer to the Parallel Write Port D output register on the next rising edge of the peripheral clock. Parallel Port D Control Register ...

  • Page 93

    Parallel Port D Drive Control Register Bit(s) Value 7:0 0 The corresponding port bit output, is driven high and low. 1 The corresponding port bit output, is open-drain. Parallel Port D Data Direction Register Bit(s) Value ...

  • Page 94

    ... The port buffer (bit 7) is written with the value of this bit. The port buffer will be 7 Write transferred to the port output register on the next rising edge of the peripheral clock 84 (PDB3R) (Address = 0x006B) Description (PDB4R) (Address = 0x006C) Description (PDB5R) (Address = 0x006D) Description (PDB6R) (Address = 0x006E) Description (PDB7R) (Address = 0x006F) Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 95

    Serial Port x Control Register Bit(s) Value 7 operation. These bits are ignored in the asynch mode clocked serial mode, start a byte receive operation clocked serial mode, start a byte transmit operation. In ...

  • Page 96

    ... Rabbit 3000 Microprocessor User’s Manual ...

  • Page 97

    ... Table 12-1. Parallel Port E Alternate Pin Functions Pin Name Interrupts PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Chapter 12 Parallel Port E 12. P ARALLEL Inputs Slave Port — /SCS — INT1B INT0B — — INT1A INT0A P E ORT Outputs I/O Strobes ...

  • Page 98

    ... PECR 0x0074 PEFR 0x0075 PEDDR 0x0077 PEB0R 0x0078 PEB1R 0x0079 PEB2R 0x007A PEB3R 0x007B PEB4R 0x007C PEB5R 0x007D PEB6R 0x007E PEB7R 0x007F Rabbit 3000 Microprocessor User’s Manual R/W Reset R/W xxxxxxxx W xx00xx00 W 00000000 W 00000000 W xxxxxxxx W xxxxxxxx W xxxxxxxx W xxxxxxxx W xxxxxxxx W xxxxxxxx ...

  • Page 99

    Dependencies 12.2.1 I/O Pins Parallel Port E uses the pins PE0 through PE7. These pins can be used individually as data inputs or outputs external I/O strobes; four of the Parallel Port E lines can be used ...

  • Page 100

    ... Parallel Port E Data Register Bit(s) Value 7:0 Read The current state of Parallel Port E pins PE7–PE0 is reported. The Parallel Port E buffer is written with this value for transfer to the Parallel Write Port E output register on the next rising edge of the peripheral clock. Parallel Port E Control Register ...

  • Page 101

    Parallel Port E Bit 0 Register Bit(s) Value 7:1 These bits are ignored. The port buffer (bit 0) is written with the value of this bit. The port buffer will be 0 Write transferred to the port output register on ...

  • Page 102

    ... The port buffer (bit 7) is written with the value of this bit. The port buffer will be 7 Write transferred to the port output register on the next rising edge of the peripheral clock 92 (PEB5R) (Address = 0x007D) Description (PEB6R) (Address = 0x007E) Description (PEB7R) (Address = 0x007F) Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 103

    Interrupt x Control Register Bit(s) Value 7:6 xx These bits are reserved for future use. 5:4 00 Parallel Port E high nibble interrupt disabled. 01 Parallel Port E high nibble interrupt on falling edge. 10 Parallel Port E high nibble ...

  • Page 104

    ... Slave port interrupts are disabled. (Write 01 Slave port interrupts use Interrupt Priority 1. only) 10 Slave port interrupts use Interrupt Priority 2. 11 Slave port interrupts use Interrupt Priority 3. * Introduced with Rabbit 3000A chip. 94 (SPCR) Description * . Rabbit 3000 Microprocessor User’s Manual (Address = 0x0024) ...

  • Page 105

    ... Input Capture Decoder × AQD2A AQD2B — × AQD1A AQD1B — × QD2A QD2B — × QD1A QD1B — ORT Outputs PWM Serial Ports A–D PWM3 — PWM2 — PWM1 — PWM0 — — — — — — CLKC — CLKD 95 ...

  • Page 106

    ... Port F Control Register Port F Function Register Port F Drive Control Register Port F Data Direction Register 96 Mnemonic I/O Address PFDR 0x0038 PFCR 0x003C PFFR 0x003D PFDCR 0X003E PFDDR 0x003F Rabbit 3000 Microprocessor User’s Manual R/W Reset R/W xxxxxxxx W xx00xx00 W xxxxxxxx W xxxxxxxx W 00000000 ...

  • Page 107

    ... Parallel Port F not used for PWM or serial clock outputs as inputs and take the precau- tion of setting up Parallel Port F before the conflicting functionality of Parallel Port A is enabled. Refer to Rabbit’s Technical Note TN228, Rabbit 3000 Parallel Port F Bug, for more information. Chapter 13 Parallel Port F Function Configure a Parallel Port F pin as a clocked serial pin ...

  • Page 108

    ... Bit(s) Value 7:0 Read The current state of Parallel Port F pins PF7–PF0 is reported. The Parallel Port F preload register is written with this value for transfer to the Write Parallel Port F output register on the next rising edge of the peripheral clock. Parallel Port F Control Register ...

  • Page 109

    Parallel Port F Drive Control Register Bit(s) Value 7:0 0 The corresponding port bit output, is driven high and low. 1 The corresponding port bit output, is open-drain. Parallel Port F Data Direction Register Bit(s) Value ...

  • Page 110

    ... Quadrature Decoder interrupts are disabled. 01 Quadrature Decoder interrupt use Interrupt Priority 1. 1:0 10 Quadrature Decoder interrupt use Interrupt Priority 2. 11 Quadrature Decoder interrupt use Interrupt Priority 3. * Introduced with Rabbit 3000A chip 100 (QDCR) (Address = 0x0091) Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 111

    ... These inputs and outputs are also used for PWM outputs and for access to the data and clock I/O of SDLC/HDLC Serial Ports E and F. Table 14-1. Parallel Port G Alternate Pin Functions Pin Name Serial Ports E–F PG7 RXE PG6 — ...

  • Page 112

    ... PGCR, where the option of updating the Parallel Port G pins can be synchro- nized to the output of Timer A1, Timer B1, or Timer B2. 102 Mnemonic I/O Address PGDR 0x0048 PGCR 0x004C PGFR 0x004D PGDCR 0x004E PGDDR 0x004F Rabbit 3000 Microprocessor User’s Manual R/W Reset R/W xxxxxxxx W xx00xx00 W xxxxxxxx W xxxxxxxx W 00000000 ...

  • Page 113

    Interrupts There are no interrupts associated with Parallel Port G. 14.3 Operation The following steps must be taken before using Parallel Port G. 1. Select the desired input/output direction for each pin via PGDDR. 2. Use PGCR to select ...

  • Page 114

    ... Parallel Port G Data Register Bit(s) Value 7:0 Read The current state of Parallel Port G pins PG7–PG0 is reported. The Parallel Port G buffer is written with this value for transfer to the Parallel Write Port G output register on the next rising edge of the peripheral clock. Parallel Port G Control Register ...

  • Page 115

    Parallel Port G Function Register Bit(s) Value 7 0 Parallel Port G pin 7 is always a parallel port input. 1 Parallel Port G pin 7 is enabled as RxE Parallel Port G pin parallel ...

  • Page 116

    ... Rabbit 3000 Microprocessor User’s Manual ...

  • Page 117

    ... Timers A2–A7 can be used to generate baud rates for Serial Ports A–F, or they can be used as general-purpose timers if the dedicated timers on the Rabbit 3000 serial ports are used. ...

  • Page 118

    ... There is one interrupt vector for Timer A and a common interrupt priority. A common status register (TACSR) has bits for Timers A1–A7 that indicate if the output pulse for that timer has taken place since the last read of the status register. These bits are cleared when the status register is read ...

  • Page 119

    Block Diagram Chapter 15 Timer A 109 ...

  • Page 120

    ... The output of Timer A does not come out directly on any of the I/O pins. It can be used to control when the output occurs on Parallel Ports D–G, and can affect the output times of Serial Ports A–F and the PWM. Timer A also affects the resolution of the Quadrature Decoder and the input capture inputs ...

  • Page 121

    ... Interrupts A Timer A interrupt can be generated whenever Timers A1–A7 decrement to zero by enabling the appropriate bit in TACSR. The interrupt request is cleared when TACSR is read. The Timer A interrupt vector is in the IIR at offset 0x0A0. It can be set as Priority TACR. 15.3 Operation The following steps explain how to set up a Timer A timer. ...

  • Page 122

    ... These bits are reserved and should be written with zero The main clock for Timer A is the peripheral clock (perclk). 1 The main clock for Timer A is the peripheral clock divided by two (perclk/2). 112 (TACSR) (Address = 0x00A0) Description (TAPR) (Address = 0x00A1) Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 123

    Timer A Control Register Bit(s) Value 7 0 Timer A7 clocked by the main Timer A clock. 1 Timer A7 clocked by the output of Timer A1 Timer A6 clocked by the main Timer A clock. 1 Timer ...

  • Page 124

    ... Processor clock from the main clock, divided by four. 110 Peripheral clock from the main clock, divided by four. Processor clock from the main clock, divided by six. 111 Peripheral clock from the main clock, divided by six. 114 (GCSR) (Address = 0x0000) Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 125

    Overview The Timer B peripheral consists of a ten-bit free running up-counter and two match registers. Timer B is driven by perclk/2, by perclk/16 the output of Timer A1. Timer B gener- ates an output pulse whenever ...

  • Page 126

    ... Dependencies 16.2.1 I/O Pins The output of Timer B does not come out directly on any of the I/O pins. It can be used to control when the output occurs on Parallel Ports D–E. 16.2.2 Clocks The timer in Timer B can be clocked by perclk/2, perclk/16 countdown Timer A1 as selected in TBCR. ...

  • Page 127

    Operation The following steps explain how to set up a Timer B countdown timer. 1. Select perclk/2, perclk/16, or countdown Timer A1 in TBCR. 2. Enable Timer B by writing bit 0 of TBCSR. 16.3.1 Handling ...

  • Page 128

    ... Timer B clocked by the perpheral clock divided by 16. 1:0 00 Timer B interrupts are disabled. 01 Timer B interrupt use Interrupt Priority 1. 10 Timer B interrupt use Interrupt Priority 2. 11 Timer B interrupt use Interrupt Priority 3. 118 (TBCSR) (Address = 0x00B0) Description (TBCR) (Address = 0x00B1) Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 129

    Timer B Count MSB x Register Bit(s) Value Two MSBs of the compare value for the Timer B comparator. This compare 7:6 Write value will be loaded into the actual comparator when the current compare detects a match. 5:0 These ...

  • Page 130

    ... Processor clock from the main clock, divided by four. 110 Peripheral clock from the main clock, divided by four. Processor clock from the main clock, divided by six. 111 Peripheral clock from the main clock, divided by six. 120 (GCSR) (Address = 0x0000) Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 131

    ... The asynchronous mode is full-duplex, while the clocked mode can be half or full-duplex. Both transmit and receive have one byte of buffering — a byte may be read while another byte is being received, or the next byte to be transmitted can be loaded while the current byte is still being transferred out ...

  • Page 132

    ... Figure 17-1. Serial Ports A – D Operation in Clocked Serial Mode In the asynchronous mode, IrDA-compliant RZI encoding can be enabled to reduce the bit widths to 3/16 the normal width (1/8 the normal width if the serial data clock is 8× instead of 16×), which allows the serial port signal to be connected directly to an IrDA transceiver. ...

  • Page 133

    ... Block Diagram Chapter 17 Serial Ports A – D 123 ...

  • Page 134

    ... SCLR 0x00E2 SCSR 0x00E3 SCCR 0x00E4 SCER 0x00E5 SDDR 0x00F0 SDAR 0x00F1 SDLR 0x00F2 SDSR 0x00F3 SDCR 0x00F4 SDER 0x00F5 Rabbit 3000 Microprocessor User’s Manual R/W Reset R/W xxxxxxxx W xxxxxxxx W xxxxxxxx R 0xx00000 W xx000000 R/W 00000000 R/W xxxxxxxx W xxxxxxxx W xxxxxxxx ...

  • Page 135

    ... PB1 Receive Clock PB1 17.2.2 Clocks The data clocks for Serial Ports A – D are based on the corresponding Timer A output and can be divided by a Timer A divider. The overall clock divider will be the value in the appropriate register plus one. 17.2.3 Other Registers Register ...

  • Page 136

    ... Serial Port A at offset 0x0C0 • Serial Port B at offset 0x0D0 • Serial Port C at offset 0x0E0 • Serial Port D at offset 0x0F0 Each of them can be set as Priority SxCR, where – D for the four serial ports. 126 Rabbit 3000 Microprocessor User’s Manual ...

  • Page 137

    ... Operation 17.3.1 Asynchronous Mode The following steps explain how to set up Serial Ports A – D for asynchronous operation. The serial ports can be used by polling the status byte, but their performance will be better with an interrupt. These instructions also apply to the asynchronous operation of Serial Ports E – ...

  • Page 138

    ... Write the desired divider value to TATxR for the appropriate serial port. 6. There are two methods to transfer a byte: write the byte to SxDR and then write 10 (or 11) to bits 6–7 of SxCR to enable the transfer; write the byte to SxAR which will automatically start the transfer. ...

  • Page 139

    ... A here ioi ld (SADR), a done: pop af ipres ret Chapter 17 Serial Ports A – save used registers ; get status ; check if byte ready in RX buffer ; save status for next check ; read byte and clear interrupt ; set bits 6-7 to 01, the other bits should ...

  • Page 140

    ... Loads the transmit buffer with an address byte, marked with a “zero” address bit, for transmission. Writing the data to this register in the clocked serial mode ...

  • Page 141

    ... The receive data register is empty—no input character is ready. There is a byte in the receive buffer. The transition from “0” to “1” sets the receiver interrupt request flip-flop. The interrupt FF is cleared when the character 1 is read from the data buffer. The interrupt FF will be immediately set again if there are more characters available in the FIFO or shift register to be transferred into the data buffer ...

  • Page 142

    ... These bits are always zero in the clocked serial mode. 132 (SASR) (Address = 0x00C3) (SBSR) (Address = 0x00D3) (SCSR) (Address = 0x00E3) (SDSR) (Address = 0x00F3) Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 143

    ... Serial Port A clock is on Parallel Port B pin 1 Serial Port B clock is on Parallel Port B pin 0 1:0 00 The serial port interrupt is disabled. 01 The serial port uses Interrupt Priority 1. 10 The serial port uses Interrupt Priority 2. Chapter 17 Serial Ports A – D (SACR) (Address = 0x00C4) (SBCR) (Address = 0x00D4) Description 133 ...

  • Page 144

    ... Serial Port D clock is on Parallel Port F pin 0 00 The serial port interrupt is disabled. 01 The serial port uses Interrupt Priority 1. 1:0 10 The serial port uses Interrupt Priority 2. 11 The serial port uses Interrupt Priority 3. 134 (SCCR) (Address = 0x00E4) (SDCR) (Address = 0x00F4) Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 145

    ... Asynchronous clock is 16× data rate. 1 Asynchronous clock is 8× data rate. 1:0 xx These bits are ignored in the asynchronous mode. Chapter 17 Serial Ports A – D (SAER) (Address = 0x00C5) (SBER) (Address = 0x00D5) (SCER) (Address = 0x00E5) (SDER) (Address = 0x00F5) ...

  • Page 146

    ... Timer A counter counts down to zero. The timer counts modulo where n is the programmed time constant. 136 (SAER) (Address = 0x00C5) (SBER) (Address = 0x00D5) (SCER) (Address = 0x00E5) (SDER) (Address = 0x00F5) Description (TAT4R) (Address = 0x00A9) (TAT5R) (Address = 0x00AB) (TAT6R) (Address = 0x00AD) (TAT7R) (Address = 0x00AF) Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 147

    ... Parallel Port D pin 5 is always a parallel port I/O pin Parallel Port D pin parallel port I/O pin. 1 Parallel Port D pin 4 drives ATxB. 3:0 x Parallel Port D pins 3:0 are always parallel port I/O pins. Chapter 17 Serial Ports A – D (PCFR) (Address = 0x0055) Description (PDFR) (Address = 0x0065) Description 137 ...

  • Page 148

    ... Rabbit 3000 Microprocessor User’s Manual ...

  • Page 149

    ... Serial Ports E and F are identical to each other, and their asynchronous operation is identi- cal to that of Serial Ports A – D except for the source of the data clock, the buffer sizes, and the transmit, receive, and clock pins. Each serial port can be used in the asynchronous or the HDLC mode with an internal or external clock ...

  • Page 150

    ... The timing of this synchronization is adjusted with each incoming transition, allowing for tracking if the two external clocks differ slightly in frequency. For more on the clock syn- chronization and data encoding, see Section 18.3.3. 18.1.1 Block Diagram 140 Rabbit 3000 Microprocessor User’s Manual ...

  • Page 151

    ... Serial Port E Extended Register Serial Port F Data Register Serial Port F Address Register Serial Port F Long Stop Register Serial Port F Status Register Serial Port F Control Register Serial Port F Extended Register Chapter 18 Serial Ports E – F Mnemonic I/O Address SEDR 0x00C8 SEAR 0x00C9 SELR ...

  • Page 152

    ... Receive Clock * Introduced with Rabbit 3000A chip. 18.2.2 Clocks The data clocks for Serial Ports E – F are based on the corresponding Timer A output and can be divided by a Timer A divider. The overall clock divider will be the value in the appropriate register plus one. 18.2.3 Other Registers ...

  • Page 153

    ... The serial port interrupt vectors are located in the IIR as follows. • Serial Port E at offset 0x1C0 • Serial Port F at offset 0x1D0 Each of them can be set as Priority SxCR, where – F for the two serial ports. Chapter 18 Serial Ports E – F 143 ...

  • Page 154

    ... The receiver will be synchronized on flag bytes and will reset the CRC. By monitoring the received bytes, decisions can be made about the incoming packet not desired (i.e not addressed to this device), writing bits 6–7 of SxCR will force the receiver back into the flag search mode. ...

  • Page 155

    ... The transmitter is not capable of sending an arbitrary number of bits, but only a multiple of bytes. However, the receiver can receive frames of any bit length. If the last “byte” in the frame is not eight bits, the receiver sets a status flag that is buffered along with this last byte. Software can then use the table below to determine the number of valid data bits in this last “ ...

  • Page 156

    ... DPLL-tracked bit-cell boundaries, so the count is shortened by either one or two counts. If the transition occurs later than expected, it means that the bit-cell boundaries are late with 146 Rabbit 3000 Microprocessor User’s Manual ...

  • Page 157

    ... DPLL to provide the extra two clocks to the receiver to assemble the data correctly. The transition is specified as follows. • In the biphase-level mode this means the transition that defines the last zero of the closing flag. • In the biphase-mark and the biphase-space modes this means the transition that defines the end of the last zero of the closing flag. Chapter 18 Serial Ports E – ...

  • Page 158

    ... DPLL needs to lengthen the count to line up the bit-cell boundaries. This corresponds to the “add one” and “add two” regions shown transition occurs before the bit-cell boundary (but after the midpoint), the DPLL needs to shorten the count to line up the bit-cell boundaries. This corresponds to the “ ...

  • Page 159

    ... Read Returns the contents of the receive buffer. Loads the transmit buffer with an address byte, marked with a “zero” address bit, Write for transmission. In the HDLC mode, the last byte of a frame must be written to this register to enable subsequent CRC and closing flag transmission. ...

  • Page 160

    ... The receive data register is empty—no input character is ready. There is a byte in the receive buffer. The transition from “0” to “1” sets the receiver interrupt request flip-flop. The interrupt FF is cleared when the 1 character is read from the data buffer. The interrupt FF will be immediately set again if there are more characters available in the FIFO or shift register to be transferred into the data buffer ...

  • Page 161

    ... The transmitter finished sending a closing flag. Data written in response to this 11 interrupt will cause at least two flags to be transmitted between frames The byte in the receiver buffer is 8 bits. 1 The byte in the receiver buffer is less than 8 bits. Chapter 18 Serial Ports E – F (SESR) (Address = 0x00CB) (SFSR) (Address = 0x00DB) Description 151 ...

  • Page 162

    ... HDLC mode with internal clock. The clock is 16× the data rate, and the DPLL is used to recover the receive clock. If necessary, the clocks are supplied as follows: 11 • Bit 4 is 0—pins PG4 and PG5(Serial Port E); pins PG0 and PG1 (Serial Port F). • Bit 4 is 1—pin PG4 (Serial Port E) and pin PG0 (Serial Port F). 1:0 00 The serial port interrupt is disabled ...

  • Page 163

    ... Asynchronous clock is 16× data rate. 1 Asynchronous clock is 8× data rate. 1:0 xx These bits are ignored in the asynchronous mode. Chapter 18 Serial Ports E – F (SEER) (Address = 0x00CD) (SFER) (Address = 0x00DD Description 153 ...

  • Page 164

    ... Timer A counter counts down to zero. The timer counts modulo where n is the programmed time constant. 154 (SEER) (Address = 0x00CD) (SFER) (Address = 0x00DD) Description (TAT2R) (Address = 0x00A5) (TAT3R) (Address = 0x00A7)) Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 165

    ... Parallel Port G pin 1 is always a parallel port input. Parallel Port G pin 1 is enabled as an SDLC/HDLC.receive clock output for Serial 1 Port Parallel Port G pin parallel port output. Parallel Port G pin 0 is enabled as an SDLC/HDLC.transmit clock output for 1 Serial Port F. Chapter 18 Serial Ports E – F (PGFR) (Address = 0x004D) Description 155 ...

  • Page 166

    ... Rabbit 3000 Microprocessor User’s Manual ...

  • Page 167

    Overview The slave port is a parallel communication port that can be used to communicate with an external master device. The slave port consists of three data input and data output regis- ters, and a status register. The data ...

  • Page 168

    ... Slave Port Data 2 Register Slave Port Status Register Slave Port Control Register 158 Mnemonic I/O Address SPD0R 0x0020 SPD1R 0x0021 SPD2R 0x0022 SPSR 0x0023 SPCR 0x0024 Rabbit 3000 Microprocessor User’s Manual R/W Reset R/W xxxxxxxx R/W xxxxxxxx R/W xxxxxxxx R 00000000 R/W 0xx00000 ...

  • Page 169

    ... Slave Port Pin(s) Signal PA0–PA7 SD0–SD7 PB7 /SLAVEATTN * PB6 /ASCS PB4–PB5 SA0–SA1 PB3 /SRD PB2 /SWR PE7 /SCS * Introduced with Rabbit 3000A chip 19.2.2 Clocks All slave port operations are based on the processor clock. 19.2.3 Interrupts If slave port interrupts are enabled, a slave port interrupt will occur on the slave device whenever the master writes to SPD0R ...

  • Page 170

    ... Operation Figure 19-1 shows a typical slave port connection between a Rabbit processor as the master and two slaves. Figure 19-1. Master/Slave Port Connections 160 Rabbit 3000 Microprocessor User’s Manual ...

  • Page 171

    ... In this setup, the slave port is used as follows: • The slave responds to the interrupt and reads the slave port data registers. • When the slave wishes to send data to the master, it writes the slave port data registers, writing SPD0R last, which enables the /SLAVEATTN signal. ...

  • Page 172

    ... Rabbit 3000 Microprocessor User’s Manual ...

  • Page 173

    ... All devices could poll the slave port status register to determine when data is present instead of relying on interrupts. • The master could write to SPD0R, triggering an interrupt on the slave. The slave could then simply write a response into SPD0R, which the master detects by polling SPSR. ...

  • Page 174

    ... Timing Diagrams Figure 19-2 shows the sequence of events when the master reads/writes the slave port registers. Figure 19-2. Slave Port R/W Timing Diagram 164 Rabbit 3000 Microprocessor User’s Manual ...

  • Page 175

    ... Low Pulse Width Ten(SRD) /SRD to SD Enable Time Ta(SRD) /SRD to SD Access Time Tdis(SRD) /SRD to SD Disable Time Tsu(SRW – SRD) /SWR High to /SRD Low Setup Time Tw(SWR) /SWR Low Pulse Width Tsu(SD) SD Setup Time Th(SD) SD Hold Time Tsu(SRD – SWR) /SRD High to /SWR Low Setup Time ...

  • Page 176

    ... Slave port write byte 1 is empty. 1 Slave port write byte 1 is full Slave port write byte 0 is empty. 1 Slave port write byte 0 is full. 166 (SPD0R) (Address = 0x0020) (SPD1R) (Address = 0x0021) (SPD2R) (Address = 0x0022) Description (SPSR) (Address = 0x0023) Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 177

    Slave Port Control Register Bit(s) Value 7 0 Program fetch as a function of the SMODE pins. 1 Ignore the SMODE pins program fetch function. 6:5 Read These bits report the state of the SMODE pins. Write These bits are ...

  • Page 178

    ... Rabbit 3000 Microprocessor User’s Manual ...

  • Page 179

    ... The same pin may be used to detect the start and stop condition—for example a rising edge could be the start condition and a falling edge could be the stop condition. The start and stop condition can also be input on separate pins. ...

  • Page 180

    ... Mnemonic I/O Address ICCSR 0x0056 ICCR 0x0057 ICT1R 0x0058 ICS1R 0x0059 ICL1R 0x005A ICM1R 0x005B ICT2R 0x005C ICS2R 0x005D ICL2R 0x005E ICM2R 0x005F Rabbit 3000 Microprocessor User’s Manual R/W Reset R/W 00000000 W xxxxxx00 W 00000000 W xxxxxxxx R xxxxxxxx R xxxxxxxx W 00000000 W xxxxxxxx R xxxxxxxx R ...

  • Page 181

    ... Because of this, there is some delay between the input transition and when an interrupt is requested, as shown below. The status bits in ICSxR are set coincident with the interrupt request and are reset when read from the ICSxR. Chapter 20 Input Capture Function Time constant for Input Capture clock. 171 ...

  • Page 182

    ... If needed, the current counter value can be read from ICLxR and LCMxR (reading from ICLxR latches the value of ICLxR, so ICLxR should always be read first) • If the counter is expected to roll over, determine if that is why the interrupt occurred by reading the status bits in ICCSR and adjusting any software counters accordingly • ...

  • Page 183

    ... Set up the counter to run continuously, latch on the stop condition, and generate an interrupt on the stop condition. 2. Set up the stop condition for the event of interest. 3. Reset the counter via ICCSR at the software start the interrupt handler, read the counter as a time duration. Chapter 20 Input Capture 173 ...

  • Page 184

    ... Normal Input Capture operation. x0 Normal Input Capture operation. Reserved for test. The Input Capture counter increments at both bit 0 and bit 8. 11 There is no carry from lower byte to higher byte. 174 (ICCSR) (Address = 0x0056) Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 185

    ... Ignore the ending input. These two bits are ignored in Counter operation. 01 The Stop condition is the rising edge of the ending input. 10 The Stop condition is the falling edge of the ending input. 11 The Stop condition is either edge of the ending input. Chapter 20 Input Capture (ICCR) (Address = 0x0057) Description (ICT1R) (Address = 0x0058) (ICT2R) ...

  • Page 186

    ... Timer A counter counts down to zero. The timer counts modulo where n is the programmed time constant. 176 (ICS1R) (Address = 0x0059) (ICS2R) (Address = 0x005D) Description (ICL1R) (Address = 0x005A) (ICL2R) (Address = 0x005E) Description (ICM1R) (Address = 0x005B) (ICM2R) (Address = 0x005F) Description (TAT8R) (Address = 0x00A6) Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 187

    Q 21.1 Overview The Rabbit 3000 has a two-channel Quadrature Decoder that accepts inputs via specific pins on Parallel Port F. Each channel has two inputs, the in-phase (I) input and the 90 degree or quadrature-phase (Q) input. An ...

  • Page 188

    ... The timing for the interrupt is shown below. Note that the status bits in the QDCSR are set coincident with the interrupt, and the interrupt and status bits are cleared by reading the QDCSR. 178 Rabbit 3000 Microprocessor User’s Manual ...

  • Page 189

    ... Introduced with Rabbit 3000A chip Chapter 21 Quadrature Decoder Mnemonic I/O Address R/W QDCSR 0x0090 QDCR 0x0091 QDC1R 0x0094 * QDC1HR 0x0095 QDC2R 0x0096 * QDC2HR 0x0097 Rabbit Rabbit 3000 3000A Reset Reset R/W xxxxxxxx W 00xx0000 00000000 R xxxxxxxx R — xxxxxxxx R xxxxxxxx R — xxxxxxxx 179 ...

  • Page 190

    ... The status bits in the QDCSR are set coincident with the interrupt request and are reset when QDCSR is read. 180 Channel 1 Channel PF1 PF0 PF3 PF2 PF5 PF4 PF7 PF6 Function Time constant for Quadrature Decoder clock Rabbit 3000 Microprocessor User’s Manual ...

  • Page 191

    ... QDCSR and adjust any software counters accordingly. This will also clear the interrupt request. • The current counter value can be read from QDCxR (and QDCxHR if the 10-bit coun- ter is enabled). 21.3.2 Example ISR A sample interrupt handler is shown below ...

  • Page 192

    ... Quadrature Decoder 1 decremented from 0x00 to 0xFF (0x3FF in 10-bit mode). 1 only) This bit is cleared by a read of this register. 1 This bit always reads as zero effect on Quadrature Decoder 1. (Write- 1 Reset Quadrature Decoder 1 to 0x00 without causing an interrupt. only) 182 (QDCSR) (Address = 0x0090) Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 193

    Quad Decode Control Register Bit(s) Value Disable Quadrature Decoder 2 inputs. Writing a new value to these bits will not 7:6 00 cause Quadrature Decoder 2 to increment or decrement. 01 This bit combination is reserved and should not be ...

  • Page 194

    ... Time constant for the Timer A counter. This time constant will take effect the 7:0 next time that the Timer A counter counts down to zero. The timer counts modulo where n is the programmed time constant. 184 (TAT10R) (Address = 0x00AA) Description Rabbit 3000 Microprocessor User’s Manual ...

  • Page 195

    P 22.1 Overview The Pulse Width Modulator (PWM) consists of a 10-bit free running counter and four width registers. A PWM output consists of a train of periodic pulses within a 1024-count frame with a duty cycle that varies ...

  • Page 196

    ... To get the exact high time, the Pulse-Width Modulator uses the two LSBs of the pulse-width register to modify the high time in each quadrant according to the table below. The “n/4” term is the base count, formed from the eight MSBs of the pulse-width register. ...

  • Page 197

    Block Diagram 22.1.2 Registers Register Name PWM LSB 0 Register PWM MSB 0 Register PWM LSB 1 Register PWM MSB 1 Register PWM LSB 2 Register PWM MSB 2 Register PWM LSB 3 Register PWM MSB 3 Register Chapter ...

  • Page 198

    ... The PWM interrupt vector is in the IIR at offset 0x170. It can be set as Priority writing to PWL0R. 188 PWM Output Pins Channel 0 PF4, PG3 Channel 1 PF5, PG7 Channel 2 PF6, PD3 Channel 3 PF7, PD7 Function Time constant for PWM clock Alternate port output selection Rabbit 3000 Microprocessor User’s Manual ...

  • Page 199

    ... Configure PWL0R to select the PWM interrupt priority and PWL1R to select PWM interrupt suppression (if an interrupt is desired). The following actions occur within the interrupt service routine. • Any PWM values may be updated. • The interrupt request should be cleared by writing to any PWM register. 22.3.2 Example ISR A sample interrupt handler is shown below. pwm_isr:: ...

  • Page 200

    ... Bit(s) Value Most significant eight bits for the Pulse Width Modulator count. With a count of 7:0 Write “n”, the PWM output will be High for “n + 1” clocks out of the 1024 clocks of the PWM counter. Timer A Time Constant 9 Register Bit(s) Value Time constant for the Timer A counter. This time constant will take effect the 7:0 next time that the Timer A counter counts down to zero ...