Z8S18010PSG Zilog, Z8S18010PSG Datasheet - Page 14

• Manufacturer Part Number: Z8S18010PSG
• Description: IC 10MHZ STATIC Z180 64-DIP
• Manufacturer: Zilog

Specifications of Z8S18010PSG

• Processor Type: Z180
• Features: Enhanced Z180
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8S180X
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: Z8S18000ZEM
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4297; Z8S18010PSG

The Z180 combines a high-performance CPU core with a
variety of system and I/O resources useful in a broad range
of applications. The CPU core consists of five functional
blocks: clock generator, bus state controller, Interrupt con-
troller, memory management unit (MMU), and the central
processing unit (CPU). The integrated I/O resources make
up the remaining four functional blocks: direct memory ac-
cess (DMA) control (2 channels), asynchronous serial com-
munication interface (ASCI, 2 channels) programmable re-
load timers (PRT, 2 channels), and a clock serial I/O
(CSI/O) channel.
an external crystal or clock input. The external clock is di-
vided by 2 or 1 and provides the timing for both internal
and external devices.
and bus-control activity associated with the CPU and some
on-chip peripherals. Also includes wait-state timing, reset
cycles, DRAM refresh, and DMA bus exchanges.
the variety of internal and external interrupts and traps to
provide the correct responses from the CPU. To maintain
compatibility with the Z80 CPU, three different interrupts
modes are supported.
map the memory used by the CPU (logically only 64KB)
into the 1-MB addressing range supported by the
Z8S180/Z8L180. The organization of the MMU object
This logic generates a system clock from
This logic monitors and prioritizes
This logic performs all of the status
The MMU allows the user to
code maintains compatibility with the Z80 CPU, while of-
fering access to an extended memory space. Accomplished
by using an effective common-area/banked-area scheme.
vide a core that is object-code compatible with the Z80
CPU. It also provides a superset of the Z80 instruction set,
including 8-bit multiplication. The core is modified to allow
many of the instructions to execute in fewer clock cycles.
speed transfers between memory and I/O devices. Transfer
operations supported are memory-to-memory, memory
to/from I/O, and I/O-to-I/O. Transfer modes supported are
request, burst, and cycle steal. DMA transfers can access
the full 1-MB address range with a block length up to 64 KB,
and can cross over 64K boundaries.
The ASCI logic provides two individual full-duplex
UARTs. Each channel includes a programmable baud rate
generator and modem control signals. The ASCI channels
can also support a multiprocessor communication format as
well as break detection and generation
of two separate channels, each containing a 16-bit counter
(timer) and count reload register. The time base for the
counters is derived from the system clock (divided by 20)
before reaching the counter. PRT channel 1 provides an op-
tional output to allow for waveform generation.
The DMA controller provides high-
The CPU is microcoded to pro-
This logic consists
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