Z8S18010PSG Zilog, Z8S18010PSG Datasheet - Page 44

• Manufacturer Part Number: Z8S18010PSG
• Description: IC 10MHZ STATIC Z180 64-DIP
• Manufacturer: Zilog

Specifications of Z8S18010PSG

• Processor Type: Z180
• Features: Enhanced Z180
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8S180X
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: Z8S18000ZEM
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4297; Z8S18010PSG

most recently received character in the
Each ASCI channel status register (
rogation of ASCI communication, error and modem control
1
and the receive data (which generated the error) is still load-
ed into the
mode, during
auto-enabled and is negated (High).
curs if the receiver finishes assembling a character but the
ever, this status bit is not set until the most recent character
received before the overrun becomes the oldest byte in the
by
auto enabled and is negated (High).
parity checking is enabled.When the
when an incoming data byte is loaded into an empty
bit in the
. If a framing or parity error occurs,
. This bit is cleared when software writes a
When an overrun occurs, the receiver does not place the
character in the shift register into the
sequent characters, until the most recent good character
enters the top of the
then writes a
is full so there is no room for the character. How-
in
.
1
and for
register. The bit may also be cleared
to
mode or
is cleared to
A parity error is detected when
to clear it.
so that
An overrun condition oc-
0
if the
by reading
if the
is set. Software
) allows inter-
from
, nor any sub-
bit in the
is still set
1
is set to
input is
to the
pin is
and
signal status, and the enabling or disabling of ASCI inter-
rupts.
parity does not match the
However, this status bit is not set until or unless the error
character becomes the oldest one in the
cleared when software writes a
mode, or on
negated (High).
when the stop bit of a character is sampled as
However, this status bit is not set until/unless the error char-
acter becomes the oldest one in the
when software writes a
ister.
(High).
1
1
ceived and
requires its request-routing field to be set to receive data
from this ASCI. That is, if
are
does not request an interrupt for
ASCI requests an interrupt when
, the Receiver requests an interrupt when a character is re-
to enable ASCI receive interrupt requests. When
, or
, if the
register is
is also cleared by
register.
is
is set, but only if neither DMA channel
1
, if the
, a character is assembled in which the
1
is also cleared by
pin is auto-enabled and is negated
and
1
to the
A framing error is detected
bit in the
pin is auto-enabled and is
1
in
are
bit in the
to the
are
,
. If
and
should be set to
or
.
, then ASCI1
mode, or on
in
is
is cleared
is set, and
bit in the
1
register.
ZiLOG
, either
.
reg-
is
is
.