Z8S18010PSG Zilog, Z8S18010PSG Datasheet - Page 49

• Manufacturer Part Number: Z8S18010PSG
• Description: IC 10MHZ STATIC Z180 64-DIP
• Manufacturer: Zilog

Specifications of Z8S18010PSG

• Processor Type: Z180
• Features: Enhanced Z180
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8S180X
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: Z8S18000ZEM
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4297; Z8S18010PSG

regardless of whether
ZiLOG
The ASCI Extension Control Registers (
the
when the pin is negated/High, the Receiver is held in a
effect on receiver operation. In either state of this bit, soft-
ware can read the state of the
ister, and the receiver interrupts on a rising edge of
the pin is negated/High, the
is forced to
no effect on the transmitter. Regardless of the state of this
bit, software can read the state of the
register.
Generator or
called
bit is
pin is divided by 16 or 64 per the
ister, to obtain the actual bit rate. In this mode, receive data
on the
are not
state. If this bit is
pin must be synchronized to the clock on the
0
pin auto-enables the
isochronous mode
, the clock from the Baud Rate Generator or
) control functions that have been added to the
pin auto-enables the ASCI0 receiver, such that
, and this bit is
pin is not required to be synchronized to a clock.
0
If this bit is
. If this bit is
pin is taken as a 1X-bit clock (sometimes
If the
). In this mode, receive data on the
1
, the state of the
1
0
, the clock from the Baud Rate
1
, the ASCI Baud Rate Generator
is an input or an output. If this
, the state of the
bits in the
bit in the
transmitter, in that when
pin in the
If this bit is
bit in the
If this bit is
pin the
-pin has no
0
, then the
register
register
0
pin has
, then
reg-
reg-
pin,
and
.
ASCIs in the Z8S180/Z8L180 family. All bits in this
register reset to
divides
and factored by a power of two (selected by the
to obtain the clock that is presented to the transmitter and
receiver and output on the
and this bit is
twice the sum of the 16-bit value (programmed into the
Time Constant registers) and 2. This mode is identical to
the operation of the baud rate generator in the
mitter sends
1
the oldest character in the
software writes a
by
pin is auto-enabled and is negated (High).
mitter holds the
The duration of the
of the PRTs or CTCs can be used to time it). This bit resets
to
mitter.
when an all-zero character with a Framing Error becomes
0
, in which state
conditions and report them in bit
, by
by 10 or 30, depending on the
1
, the Baud Rate Generator divides
0
.
0
to the
s under the control of bit
If this bit and bit 2 are both
pin Low to send a
If this bit is
The receiver sets this read-only bit to
mode, and for
carries the serial output of the trans-
is under software control (one
bit in
pin. If
. The bit is cleared when
1
, the receiver detects
1
, and the trans-
bit in
, if the
register, also
0
are not
1
.
, the trans-
condition.
.
bits),
by
,
,