Z85C3010PSG Zilog, Z85C3010PSG Datasheet
Z85C3010PSG
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Z85C3010PSG Summary of contents
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Chapter 1. General Description 1.1 Introduction .................................................................................................................................... 1-1 1.2 SCC’s Capabilities ......................................................................................................................... 1-2 1.3 Block Diagram ............................................................................................................................... 1-4 1.4 Pin Descriptions ............................................................................................................................. 1-5 1.4.1 Pins Common to both Z85X30 and Z80X30 .................................................................... 1-7 1.4.2 Pin Descriptions, (Z85X30 Only) ...................................................................................... 1-8 ...
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SCC™/ESCC™ User’s Manual Table of Contents Chapter 3. SCC/ESCC Ancillary Support Circuitry 3.1 Introduction .................................................................................................................................... 3-1 3.2 Baud Rate Generator ..................................................................................................................... 3-1 3.3 Data Encoding/Decoding ............................................................................................................... 3-4 3.4 DPLL Digital Phase-Locked Loop .................................................................................................. 3-7 3.4.1 DPLL Operation in the NRZI ...
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... Interfacing Z80 CPUs to the Z8500 Peripheral Family ......................................................................... 6-1 The Z180™ Interfaced with the SCC at MHZ........................................................................................ 6-34 The Zilog Datacom Family with the 80186 CPU .................................................................................. 6-59 SCC in Binary Synchronous Communications ...................................................................................... 6-79 Serial Communication Controller (SCC Using SCC with Z8000 in SDLC Protocol6-105 Boost Your System Performance Using The Zilog ESCC Technical Considerations When Implementing LocalTalk Link Access Protocol ...
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Chapter 1 Figure 1-1. SCC Block Diagram .............................................................................................................................. 1-4 Figure 1-2. Z85X30 Pin Functions .......................................................................................................................... 1-5 Figure 1-3. Z80X30 Pin Functions .......................................................................................................................... 1-6 Figure 1-4. Z85X30 DIP Pin Assignments .............................................................................................................. 1-6 Figure 1-5. Z85X30 PLCC Pin Assignments ........................................................................................................... 1-6 Figure ...
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Figure 2-27. Wait On Receive Timing ..................................................................................................................... 2-35 Figure 2-28. Transmit Request Assertion ............................................................................................................... 2-36 Figure 2-29. Z80X30 Transmit Request Release ................................................................................................... 2-37 Figure 2-30. Z85X30 Transmit Request Release ................................................................................................... 2-37 Figure 2-31. /DTR//REQ Deassertion Timing ......................................................................................................... 2-38 Figure 2-32. ...
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SCC™/ESCC™ User’s Manual Tables of Contents Figure 5-6. Write Register 4 .................................................................................................................................... 5-8 Figure 5-7. Write Register 5 .................................................................................................................................... 5-9 Figure 5-8. Write Register 6 .................................................................................................................................. 5-11 Figure 5-9. Write Register 7 .................................................................................................................................. 5-11 Figure 5-10. Write Register 7 Prime ...
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Chapter 2 Table 2-1. Z80X30 Register Map (Shift Left Mode) ................................................................................................... 2-6 Table 2-2. Z80X30 Register Map (Shift Right Mode) ................................................................................................. 2-7 Table 2-3. Z80230 SDLC/HDLC Enhancement Options ........................................................................................... 2-8 Table 2-4. Z80X30 Register Reset Values ................................................................................................................ 2-9 Table 2-5. ...
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Table 5-8. Receive Clock Source ............................................................................................................................ 5-18 Table 5-9. Transmit Clock Source ........................................................................................................................... 5-18 Table 5-10. Transmit External Control Selection ....................................................................................................... 5-18 Table 5-11. I-Field Bit Selection (8 Bits Only) ............................................................................................................ 5-24 Table 5-12. Bits per Character Residue Decoding .................................................................................................... ...
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... INTRODUCTION The Zilog SCC Serial Communication Controller is a dual channel, multiprotocol data communication peripheral de- signed for use with 8- and 16-bit microprocessors. The SCC functions as a serial-to-parallel, parallel-to-serial con- verter/controller. The SCC can be software-configured to satisfy a wide variety of serial communications applica- tions. The device contains a variety of new, sophisticated ...
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... SCC™/ESCC™ User’s Manual General Description 1.2 SCC’S CAPABILITIES The NMOS version of the SCC is Zilog’s original device. The design is based on the Z80 SIO architecture. If you are familiar with the Z80 SIO, the SCC can be treated as an SIO with support circuitry such as DPLL, BRG, etc ...
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The Z85C30 CMOS SCC has added new features, while maintaining 100% hardware/software compatibility. It has the following new features: New programmable WR7' (write register 7 prime) to enable new features. Improvements to support SDLC mode of synchronous communication: – Improved ...
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SCC™/ESCC™ User’s Manual General Description 1.3 BLOCK DIAGRAM Figure 1-1 has the block diagram of the SCC. Note that the depth of the FIFO differs depending on the version. The 10X19 SDLC Frame Status FIFO is not available on the ...
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PIN DESCRIPTIONS The SCC pins are divided into seven functional groups: Address/Data, Bus Timing and Reset, Device Control, In- terrupt, Serial Data (both channels), Peripheral Control (both channels), and Clocks (both channels). Figures 1-2 and 1-3 show the pins ...
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SCC™/ESCC™ User’s Manual General Description 1.4 PIN DESCRIPTIONS (Continued) Address Data Bus Bus Timing and Reset Control Interrupt /INT 5 IEO 6 IEI 7 /INTACK 8 VCC 9 /W//REQA 10 Z85X30 /SYNCA ...
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AD1 1 AD3 2 AD5 3 AD7 4 /INT 5 IEO 6 IEI 7 /INTACK 8 VCC 9 /W//REQA 10 Z80X30 /SYNCA 11 /RTxCA 12 RxDA 13 /TRxCA 14 TxDA 15 /DTR//REQA 16 /RTSA 17 /CTSA 18 /DCDA 19 PCLK ...
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SCC™/ESCC™ User’s Manual General Description 1.4 PIN DESCRIPTIONS (Continued) receive clock cycle in which the synchronous condition is not latched. These outputs are active each time a synchro- nization pattern is recognized (regardless of character boundaries). In SDLC mode, the ...
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... R//W. Read//Write (input, read active High). This signal specifies whether the operation to be performed is a read or a write. © 1998 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. ...
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INTRODUCTION This chapter covers the system interface requirements with the SCC. Timing requirements for both devices are described in a general sense here, and the user should re- fer to the SCC Product Specification for detailed AC/DC parametric requirements. ...
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SCC™/ESCC™ User’s Manual Interfacing the SCC/ESCC 2.2 Z80X30 INTERFACE TIMING (Continued) 2.2.1 Z80X30 Read Cycle Timing The read cycle timing for the Z80X30 is shown in Figure 2-1. The register address on AD7-AD0, as well as the state of /CS0 ...
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Z80X30 Write Cycle Timing The write cycle timing for the Z80X30 is shown in Figure 2-2. The register address on AD7-AD0, as well as the state of /CS0 and /INTACK, are latched by the rising edge of /AS. R//W ...
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SCC™/ESCC™ User’s Manual Interfacing the SCC/ESCC 2.2 Z80X30 INTERFACE TIMING (Continued) 2.2.3 Z80X30 Interrupt Acknowledge Cycle Timing The interrupt acknowledge cycle timing for the Z80X30 is shown in Figure 2-3. The address on AD7-AD0 and the state of /CS0 and ...
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The Z80X30 samples the state of /INTACK on the rising edge of /AS, and AC parameters #7 and #8 specify the set- up and hold-time requirements. Between the rising edge of /AS and the falling edge of /DS, the internal ...
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SCC™/ESCC™ User’s Manual Interfacing the SCC/ESCC 2.2 Z80X30 INTERFACE TIMING (Continued) Table 2-1. Z80X30 Register Map (Shift Left Mode) AD5 AD4 AD3 AD2 ...
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Table 2-2. Z80X30 Register Map (Shift Right Mode) AD4 AD3 AD2 AD1 ...
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SCC™/ESCC™ User’s Manual Interfacing the SCC/ESCC 2.2 Z80X30 INTERFACE TIMING (Continued) 2.2.5 Z80C30 Register Enhancement The Z80C30 has an enhancement to the NMOS Z8030 register set, which is the addition of a 10x19 SDLC Frame Status FIFO. When WR15 bit ...
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Z80X30 Reset The Z80X30 may be reset by either a hardware or software reset. Hardware reset occurs when /AS and /DS are both Low at the same time, which is normally an illegal condi- tion. As long as both ...
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SCC™/ESCC™ User’s Manual Interfacing the SCC/ESCC 2.3 Z85X30 INTERFACE TIMING Two control signals, /RD and /WR, are used by the Z85X30 to time bus transactions. In addition, four other control signals, /CE, D//C, A//B and /INTACK, are used to control ...
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Z85X30 Write Cycle Timing The write cycle timing for the Z85X30 is shown in Figure 2- 6. The address on A//B and D//C, as well as the data on D7-D0, is latched by the coincidence of /WR and /CE ...
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SCC™/ESCC™ User’s Manual Interfacing the SCC/ESCC 2.3 Z85X30 INTERFACE TIMING (Continued) Between the time /INTACK is first sampled Low and the time /RD falls, the internal and external IEI/IEO daisy chain settles (AC parameter #38 TdIAI(RD) Note 5). A system ...
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A//B PNT2 PNT1 PNT0 ...
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SCC™/ESCC™ User’s Manual Interfacing the SCC/ESCC 2.3 Z85X30 INTERFACE TIMING (Continued) 2.3.5 Z85C30 Register Enhancement The Z85C30 has an enhancement to the NMOS Z8530 register set, which is the addition of a 10x19 SDLC Frame Status FIFO. When WR15 bit ...
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Z85X30 Reset The Z85X30 may be reset by either a hardware or software reset. Hardware reset occurs when /WR and /RD are both Low at the same time, which is normally an illegal condi- tion. As long as both ...
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SCC™/ESCC™ User’s Manual Interfacing the SCC/ESCC 2.4 INTERFACE PROGRAMMING (Continued) 2.4.2 Polling This is the simplest mode to implement. The software must poll the SCC to determine when data input or out- put from the SCC. In ...
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ESCC: The receive interrupt request is either caused by a re- ceive character available or a special condition. When the receive character available interrupt is generated dependent on WR7' bit D3. If WR7' D3=0, the re- ceive character ...
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SCC™/ESCC™ User’s Manual Interfacing the SCC/ESCC 2.4 INTERFACE PROGRAMMING (Continued) 2.4.4.1 Master Interrupt Enable Bit The Master Interrupt Enable (MIE) bit, WR9 D3, must be set to enable the SCC to generate interrupts. The MIE bit should be set after ...
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Daisy-Chain Resolution The six sources of interrupt in the SCC are prioritized in a fixed order via a daisy chain; provision is made, via the IEI and IEO pins, for use of an external daisy chain as well. All ...
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SCC™/ESCC™ User’s Manual Interfacing the SCC/ESCC 2.4 INTERFACE PROGRAMMING (Continued) No Figure 2-13. Interrupt Flow Chart (for each interrupt source). 2-20 Start Interrupt No Condition Exits? Yes Specific No Interrupt Enable (IEx=1)? Yes Interrupt Pendi Set (IP=1) Master No Interrupt ...
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Interrupt Acknowledge The SCC is flexible with its interrupt method. The interrupt may be acknowledged with a vector transferred, acknowl- edged without a vector, or not acknowledged at all. 2.4.6.1 Interrupt Without Acknowledge In this mode, the Interrupt Acknowledge ...
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SCC™/ESCC™ User’s Manual Interfacing the SCC/ESCC 2.4 INTERFACE PROGRAMMING (Continued) WR1 Figure 2-14. Write Register 1 Receive Interrupt Mode Control 2.4.7.1 Receive Interrupt on the ESCC On the ESCC, one other bit, WR7' bit D2, also affects ...
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When these bits indicate that a received character has reached the exit location of the FIFO, the status in RR1 should be checked and then the data should be read. If status checked, it must be done ...
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SCC™/ESCC™ User’s Manual Interfacing the SCC/ESCC 2.4 INTERFACE PROGRAMMING (Continued) by not generating the interrupt until after the byte has been read and then locking the FIFO, only one status read is necessary. A DMA can be used to do ...
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Transmit Interrupts and Transmit Buffer Empty Bit Transmit interrupts are controlled by Transmit Interrupt Enable bit (D1) in WR1. If the interrupt capabilities of the SCC are not required, polling may be used. This is select disabling ...
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SCC™/ESCC™ User’s Manual Interfacing the SCC/ESCC 2.4 INTERFACE PROGRAMMING (Continued) bit D5 nor the transmit interrupt status, and will respond exactly the same way as mentioned above. Figure 2-17 il- lustrates when the TBE bit will become set. Note: When ...
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Opening Flag TBE=0 Figure 2-17. Transmit Buffer Empty Bit Status For ESCC For Both WR7' and WR7' D5=0 Opening Flag No Transmit Interrupt TxIP = 0 Figure 2-18. Transmit Interrupt Status When WR7' D5=0 For ESCC ...
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SCC™/ESCC™ User’s Manual Interfacing the SCC/ESCC 2.4 INTERFACE PROGRAMMING (Continued) 2.4.8.3 Transmit Interrupt and Tx Underrun/EOM bit in synchronous modes As described in the section above, the behavior of the NMOS/CMOS version and the ESCC is slightly different, particularly at ...
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Last Data -1 TBE Tx Underrun /EOM Indicating CRC get loaded TxIP TxIP Reset Command to Clear Tx Interrupt Figure 2-21. Operation of TBE, Tx Underrun/EOM and TxIP on ESCC An example flowchart for processing an end of packet is ...
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SCC™/ESCC™ User’s Manual Interfacing the SCC/ESCC 2.4 INTERFACE PROGRAMMING (Continued) ESCC Write data for next packet (max. 4 Bytes) Figure 2-22. Flowchart example of processing an end of packet 2-30 START Write Last Data No TxIP=1 ? (TBE=1) Yes Issue ...
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External/Status Interrupts Each channel has six external/status interrupt conditions: BRG Zero Count, Data Carrier Detect, Sync/Hunt, Clear to Send, Tx Underrun/EOM, and Break/Abort. The master enable for external/status interrupts WR1, and the individual enable bits are ...
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SCC™/ESCC™ User’s Manual Interfacing the SCC/ESCC 2.4 INTERFACE PROGRAMMING (Continued) Because the latches close on the current status, but give no indication of change, the processor must maintain a copy of RR0 in memory. When the SCC generates an Ex- ...
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External Sync mode is illegal, but the re- sult will be the same. In Synchronous modes other than SDLC, the Sync/Hunt reports the Hunt state of the receiver. Hunt mode is en- tered when the processor issues ...
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SCC™/ESCC™ User’s Manual Interfacing the SCC/ESCC 2.5 BLOCK/DMA TRANSFER (Continued) / Buffer Tx Buffer Empty /W//REQ (=WAIT) This allows the use of a block move instruction to transfer the transmit data. In the case of the ...
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Wait On Receive The Wait On Receive function is selected by setting D6 or WR1 WR1 to 1, and then enabling the function by setting D7 of WR1 this mode, the /W//REQ ...
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SCC™/ESCC™ User’s Manual Interfacing the SCC/ESCC 2.5 BLOCK/DMA TRANSFER (Continued) 2.5.2 DMA Requests The two DMA request pins /W//REQ and /DTR//REQ can be programmed for DMA requests. The /W//REQ pin is used as either a transmit or a receive request, ...
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With only one exception, the /REQ pin directly follows the state of the transmit buffer (for the ESCC as programmed by WR7' D5) in this mode. The SCC generates only one falling edge on /REQ per character requested and the ...
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SCC™/ESCC™ User’s Manual Interfacing the SCC/ESCC 2.5 BLOCK/DMA TRANSFER (Continued) 2.5.2.3 DMA Request On Transmit (using /DTR//REQ) A second Request on Transmit function is available on the /DTR//REQ pin. This mode is selected by setting D2 of WR14 to 1. ...
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In the Request mode, /REQ will follow the state of the transmit buffer even though the transmitter is disabled. Thus, if /REQ is enabled before the transmitter is enabled, the DMA may write data to the SCC before the transmitter ...
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SCC™/ESCC™ User’s Manual Interfacing the SCC/ESCC 2.5 BLOCK/DMA TRANSFER (Continued) Once the FIFO is locked, it allows the checking of the Re- ceive Error FIFO (RR1) to find the cause of the error. Lock- ing the data FIFO, therefore, stops ...
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TEST FUNCTIONS The SCC contains two other features useful for diagnostic purposes, controlled by bits in WR14. They are Local Loopback and Auto Echo. 2.6.1 Local Loopback Local Loopback is selected when WR14 bit D4 is set to 1. ...
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UM010901-0601 ...
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INTRODUCTION The serial channels of the SCC are supported by ancillary circuitry for generating clocks and performing data encod- ing and decoding. This chapter presents a description of these functional blocks. Note to ESCC/CMOS Users: The maximum input fre- ...
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SCC™/ESCC™ User’s Manual SCC/ESCC Ancillary Support Circuitry 3.2 BAUD RATE GENERATOR (Continued) The time-constant can be changed at any time, but the new value does not take effect until the next load of the counter (i.e., after zero count is ...
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The formulas relating the baud rate to the time-constant and vice versa are shown below. Clock Frequency Time Constant = 2 x (Clock Mode) x (Baud Rate) Clock Frequency Baud Rate = 2 x (Clock Mode) x (Time Constant+ 2) ...
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SCC™/ESCC™ User’s Manual SCC/ESCC Ancillary Support Circuitry 3.3 DATA ENCODING/DECODING Data encoding is utilized to allow the transmission of clock and data information over the same medium. This saves the need to transmit clock and data over separate medium as ...
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NRZ (Non-Return to Zero). In NRZ, encoding rep- resented by a High level and represented by a Low level. In this encoding method, only a minimal amount of clocking information is available in the ...
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SCC™/ESCC™ User’s Manual SCC/ESCC Ancillary Support Circuitry 3.3 DATA ENCODING/DECODING (Continued) NRZ Transmit Clock Transmit Clock NRZ 3 Figure 3-4. Manchester Encoding Circuit 3 5 Manchester 4 UM010901-0601 ...
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DPLL DIGITAL PHASE-LOCKED LOOP Each channel of the SCC contains a digital phase-locked loop that can be used to recover clock information from a data stream with NRZI, FM, NRZ, or Manchester encod- ing. The DPLL is driven by ...
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SCC™/ESCC™ User’s Manual SCC/ESCC Ancillary Support Circuitry 3.4 DPLL DIGITAL PHASE-LOCKED LOOP (Continued) 3.4.1 DPLL Operation in the NRZI Mode To operate in NRZI mode, the DPLL must be supplied with a clock that is 32 times the data rate. ...
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Receive Data DPLL Output Correction + Windows Count 32 32 Length 3.4.2 DPLL Operation in the FM Modes To operate in FM mode, the DPLL must be supplied with a clock that is 16 times the data rate. ...
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SCC™/ESCC™ User’s Manual SCC/ESCC Ancillary Support Circuitry 3.4 DPLL DIGITAL PHASE-LOCKED LOOP (Continued mode, the transmit clock and receive clock outputs from the DPLL are not in phase. This is necessary to make the transmit and receive bit ...
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The output of the transmit clock derived from this counter is available to the /TRxC pin when the DPLL output is selected as the transmit clock source. Care must be taken using ESCC in SDLC Loop mode with the DPLL. ...
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SCC™/ESCC™ User’s Manual SCC/ESCC Ancillary Support Circuitry 3.5 CLOCK SELECTION (Continued) 2. The x1 mode in Asynchronous mode is a combination of both synchronous and asynchronous transmission. The data is clocked by a common timing base, but characters are still ...
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External Crystal Figure 3-11. Async Clock Setup Using an External Crystal WR11 UM010901-0601 /SYNC Pin B 16x R Output G /RTxC Pin SCC WR14 /TRxC OUT = BRG Output /TRxC ...
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SCC™/ESCC™ User’s Manual SCC/ESCC Ancillary Support Circuitry 3.6 CRYSTAL OSCILLATOR (Continued) Figure 3-13 shows the use of the DPLL to derive a 1x clock from the data. In this example: The DPLL clock input = BRG output (x16 the data ...
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INTRODUCTION The SCC provides two independent, full-duplex channels programmable for use in any common asynchronous or synchronous data communication protocol. The data com- munication protocols handled by the SCC are: Asynchronous mode: Asynchronous (x16, x32, or x64 clock Isochronous ...
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SCC™/ESCC™ User’s Manual Data Communication Modes 4.1 INTRODUCTION (Continued) For asynchronous data, the Transmit Shift register is for- matted with start and stop bits along with the data; option- ally with parity information bit. The formatted character is shifted out ...
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Incoming data is routed through one of several paths de- pending on the mode and character length. In Asynchro- nous mode, serial data enters the 3-bit delay if a character length of seven or eight bits is selected ...
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SCC™/ESCC™ User’s Manual Data Communication Modes 4.2 ASYNCHRONOUS MODE (Continued) The transmission of a character begins when the line makes a transition from the 1 state (or MARK condition) to the 0 state (or SPACE condition). This transition is the ...
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Table 4-2. Transmit Bits per Character Bit 7 Bit Note: For five or less bits per character selection in WR5, the following encoding is used in the data sent to the ...
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SCC™/ESCC™ User’s Manual Data Communication Modes 4.2 ASYNCHRONOUS MODE (Continued) bit, bit D0 of RR1, can be polled to determine when the last bit of transmit data has cleared the TxD pin. The number of transmit interrupts can be minimized ...
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That is, if Auto Enables is on and the /DCD pin is High, the receiver is disabled; while the /DCD pin is low, the receiver is enabled. Received characters are assembled, checked for errors, and moved to the receive ...
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SCC™/ESCC™ User’s Manual Data Communication Modes 4.3 BYTE-ORIENTED SYNCHRONOUS MODE The SCC supports three byte-oriented synchronous proto- cols. They are: monosynchronous, bisynchronous, and ex- ternal synchronous. In synchronous communications, the bit cell boundaries are referenced to a clock signal common ...
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D0 of WR10. Monosync and Bisync modes require clocking information to be transmitted along with the data either by a method of encoding data that ...
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SCC™/ESCC™ User’s Manual Data Communication Modes 4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued) Once the buffer becomes empty, the Tx CRC Enable bit is written for the next character. Enabling the CRC generator is not sufficient to control the transmission of the ...
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Table 4-6. Sync Character Length Selection Sync Length WR4,D5 WR4,D4 6 bits 0 8 bits 0 12 bits 0 16 bits 0 The arrangement of the sync character in WR6 and WR7 is shown in Figure 4-5. For those applications ...
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SCC™/ESCC™ User’s Manual Data Communication Modes 4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued) In all cases except External Sync mode, the /SYNC pin is an output that is driven Low by the SCC to signal that a sync character has been received. ...
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Change from Five to Eight Change from Eight to Five Either of two CRC polynomials are used in Synchronous modes, selected by bit D2 in WR5. If this bit is set to 1, the CRC-16 polynomial is used, if this ...
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SCC™/ESCC™ User’s Manual Data Communication Modes 4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued) Receive Data Before A is received, the receiver is in Hunt mode and the CRC is disabled. When the receive shift register compared with ...
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Modem Controls two modem control signals asso- ciated with the receiver are available in Synchronous modes: /DTR//REQ and /DCD. The /DTR//REQ pin carries the inverted state of the DTR bit (D7) in WR5 unless this pin has been ...
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SCC™/ESCC™ User’s Manual Data Communication Modes 4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued (Sync) (Data1) (Data2) Note: No CRC Calculation on "D" Direction of Data Stage Coming into SCC ...
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Table 4-8. Initializing the Receiver in Character-Oriented Mode Bit Number Reg WR4 WR3 WR5 WR6 WR7 WR10 WR3 r ...
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SCC™/ESCC™ User’s Manual Data Communication Modes 4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued transmitted, the Send Break bit (D4) in WR5 is set to 1. The transmitter is now idling but is still placed in the transmitter to receiver synchronization ...
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The information field is not restricted in format or content and can be of any reasonable length (including zero). Its maximum length is that which is expected to ...
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SCC™/ESCC™ User’s Manual Data Communication Modes 4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued) Section 2.4.8 “Transmit Interrupts and Transmit Buffer Empty bit”. The character length may be changed on the fly, but the desired length must be selected before the character is ...
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CRC. In this paragraph the term “completely sent” means shifted out of the Transmit Shift register, not shifted out of the zero inserter, which is an additional ...
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SCC™/ESCC™ User’s Manual Data Communication Modes 4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued) Hence, on the ESCC, there is no need to wait for the 2nd TxIP bit to set before writing data for the next packet which reduces the overhead. Auto ...
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Enter Hunt mode command in WR3. This bit (D4 command, and writing has no effect. The Hunt status of the receiver is reported by the Sync/Hunt bit in RR0. ...
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SCC™/ESCC™ User’s Manual Data Communication Modes 4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued) Change from Five to Eight Change from Eight to Five Most bit-oriented protocols allow an arbitrary number of bits between opening and closing flags. The SCC allows for this ...
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As an example of how the codes are interpreted, consider the case of eight bits per character and a residue code of 101. The number of valid bits for the previous, second previous, and third previous bytes are 0, 7, ...
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SCC™/ESCC™ User’s Manual Data Communication Modes 4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued) selected, the processor must issue an Error Reset com- mand in WR0 to unlock the Receive FIFO. In addition to searching the data stream for flags, the re- ceiver ...
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SDLC Frame Status FIFO This feature is not available on the NMOS version. On the CMOS version and the ESCC, the ability to receive high speed back-to-back SDLC frames is maximized by a 10-bit deep by 19-bit wide status ...
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SCC™/ESCC™ User’s Manual Data Communication Modes 4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued) SCC Status Reg Residue Bits(3) RR1 Overrun, CRC Error 5 Bits 6-Bit MUX 2 Bits 6 Bits Interface to SCC In SDLC Mode the following definitions apply. - All ...
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Enable/Disable. The frame status FIFO is enabled when WR15 bit D2 is set and the CMOS/ESCC is in the SDLC/HDLC mode. Otherwise, the status register con- tents bypass the FIFO and go directly to the bus interface (the FIFO pointer ...
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SCC™/ESCC™ User’s Manual Data Communication Modes 4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued) When a character with a special receive condition other than EOF is received (receive overrun, or parity), a special receive condition interrupt is generated after the character is read ...
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If SDLC loop is deselected, the SCC is designed to exit from the loop gracefully. When the SDLC Loop mode is de- selected by writing to WR10, the SCC waits until the next polling cycle to remove the one-bit time ...
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SCC™/ESCC™ User’s Manual Data Communication Modes 4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued) 4.4.4.3 SDLC Loop Initialization The initialization sequence for the SCC in SDLC Loop mode is similar to the sequence used in SDLC mode, ex- cept that it is longer. ...
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INTRODUCTION This section describes the functions of the various bits in the registers of the SCC (Tables 5-1 and 5-2). Reserved bits are not used in this implementation of the device and may or may not be physically present ...
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SCC™/ESCC™ User’s Manual Register Descriptions 5.1 INTRODUCTION (Continued) Among these registers, WR9 (Master Interrupt Control and Reset register) can be accessed through either channel. The RR2 (Interrupt Vector register) returns the interrupt vector modified by status, if read from Channel ...
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Write Register 0 (non-multiplexed bus mode ...
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SCC™/ESCC™ User’s Manual Register Descriptions 5.1 INTRODUCTION (Continued) Reset Tx Interrupt Pending Command (101). This com- mand is used in cases where there are no more characters to be sent; e.g., at the end of a message. This command prevents ...
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A//B PNT2 PNT1 ...
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SCC™/ESCC™ User’s Manual Register Descriptions 5.1 INTRODUCTION (Continued) When programmed to 1, this bit allows the Wait/Request function to follow the state of the receive buffer. Thus, de- pending on the state of bit 6, the /W//REQ pin is active ...
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Write Register 2 (Interrupt Vector) WR2 is the interrupt vector register. Only one vector register exists in the SCC, and it can be accessed through either channel. The interrupt vector can be modified by status information. This is controlled ...
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SCC™/ESCC™ User’s Manual Register Descriptions 5.1 INTRODUCTION (Continued) This bit is internally set SDLC mode and the SCC calculates the CRC on all bits except zeros inserted be- tween the opening and closing flags. This bit is ...
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Mode (11). The clock rate is 64 times the data rate. With this bit combination in External Sync mode, both the receiver and transmitter are placed in SDLC mode. The only variation from normal SDLC operation is that the ...
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SCC™/ESCC™ User’s Manual Register Descriptions 5.1 INTRODUCTION (Continued) Bits 6 and 5: Transmit Bits/Character select bits 1 and 0 These bits control the number of bits in each byte trans- ferred to the transmit buffer. Bits sent must be right ...
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Write Register Sync7 Sync6 Sync1 Sync0 Sync7 Sync6 Sync3 Sync2 ADR7 ADR6 ADR7 ADR6 5.2.8 Write Register 7 (Sync Character or SDLC Flag) WR7 is programmed to contain the receive sync ...
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SCC™/ESCC™ User’s Manual Register Descriptions 5.1 INTRODUCTION (Continued) 5.2.9 Write Register 7 Prime (ESCC only) This Register is used only with the ESCC. Write Register 7 Prime is located at the same address as Write Register 7. This register is ...
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Write Register 7 Prime (85C30 only) This Register is used only with the CMOS 85C30 SCC. WR7' is written to by first setting bit D0 of WR15 to 1, and pointing to WR7 as normal. All writes to register ...
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SCC™/ESCC™ User’s Manual Register Descriptions 5.1 INTRODUCTION (Continued) 5.2.12 Write Register 9 (Master Interrupt Control) WR9 is the Master Interrupt Control register and contains the Reset command bits. Only one WR9 exists in the SCC and is accessed from either ...
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Bit 0: Vector Includes Status control bit The Vector Includes Status Bit controls whether or not the SCC includes status information in the vector it places on the bus in response to an interrupt acknowledge cycle. If this bit is ...
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SCC™/ESCC™ User’s Manual Register Descriptions 5.1 INTRODUCTION (Continued) Data 1 NRZ NRZI FM1 FM0 Manchester Bit 4: Go-Active-On-Poll control bit When Loop mode is first selected during SDLC operation, the SCC connects RxD to TxD with only gate delays in ...
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On the ESCC and 85C30 with the Automatic TX SDLC Flag mode enabled (WR7', D0=1), this bit can be left as mark idle. It will send an opening flag automatically, as well as sending a closing flag followed by mark ...
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SCC™/ESCC™ User’s Manual Register Descriptions 5.1 INTRODUCTION (Continued) Table 5-8. Receive Clock Source Bit 6 Bit 5 Receive Clock 0 0 /RTxC Pin 0 1 /TRxC Pin Output 1 1 DPLL Output Bits 4 and 3: Transmit ...
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Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) WR13 contains the upper byte of the time constant for the baud rate generator. Bit positions for WR13 are shown in Figure 5-16. Write Register ...
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SCC™/ESCC™ User’s Manual Register Descriptions 5.1 INTRODUCTION (Continued) Set Source to BRG Command (100). Issuing this com- mand forces the clock for the DPLL to come from the out- put of the BRG. Set Source to /RTxC Command (101). Issuing ...
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Bit 7: Brea/Abort Interrupt Enable If this bit is set change in the Break/Abort status of the receiver causes an External/Status interrupt. This bit is set by a channel or hardware reset. Bit 6: Transmit Underrun/EOM Interrupt ...
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SCC™/ESCC™ User’s Manual Register Descriptions 5.3 READ REGISTERS (Continued) Bit 7: Break/Abort status In the Asynchronous mode, this bit is set when a Break se- quence (null character plus framing error) is detected in the receive data stream. This bit ...
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External/Status interrupt. Any odd number of transitions on the /DCD pin while another External/Status interrupt condition. If the DCD IE is reset, this bit merely re- ports the current, unlatched state of the /DCD pin. Bit 2: TX ...
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SCC™/ESCC™ User’s Manual Register Descriptions 5.3 READ REGISTERS (Continued) Also, a Special Receive Condition vector is returned, caused by the overrun characters and all subsequent char- acters received until the Error Reset command is issued. On the CMOS and ESCC, ...
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Read Register Modified In B Channel Figure 5-21. Read Register 2 5.3.4 Read Register 3 RR3 is the interrupt Pending register. The status of each of the interrupt Pending bits ...
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SCC™/ESCC™ User’s Manual Register Descriptions 5.3 READ REGISTERS (Continued) * Read Register BC8 BC9 BC10 BC11 BC12 BC13 FDA: FIFO Data Available 1 = Status Reads from FIFO 0 = Status ...
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Read Register 11 (ESCC and 85C30 Only) On the ESCC, Read Register 11 reflects the contents of Write Register 10 provided the Extended Read option has been enabled. Otherwise, this register returns an image of RR15. On the NMOS/CMOS ...
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... The hardware interface consists of three basic groups of signals; data bus, system control, and interrupt control, described below. For more detailed signal information, refer to Zilog’s DataBook, Universal Peripherals. Data Bus Signals D7-D0. Data Bus (bidirectional tri-state). This bus transfers data between the CPU and the peripherals. ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family CPU HARDWARE INTERFACING (Continued) Z80 ® Interrupt Daisy-Chain Operation In the Z80 peripherals, both the IP and IUS bits control the IEO line and the lower portion of the ...
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Write Cycle Timing Figure 2 illustrates the Z8500 Write cycle timing. All register addresses and /INTACK must remain stable throughout the cycle. If /CE goes active after /WR goes UM010901-0601 Interfacing Z80 Figure 1. Z8500 Peripheral I/O Read Cycle Timing ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family PERIPHERAL INTERRUPT OPERATION Understanding peripheral interrupt operation requires a basic knowledge of the Interrupt Pending (IP) and Interrupt Under Service (IUS) bits in relation to the daisy chain. Both ...
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INPUT/OUTPUT CYCLES Although Z8500 peripherals are designed universal as possible, certain timing parameters differ from the standard Z80 timing. The following sections discuss the I/O interface for each of the Z80 CPUs and the Z8500 peripherals. Figure ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family INPUT/OUTPUT CYCLES (Continued) Worst Case 6. TsA(WR) Address to /WR to Low Setup 1. TsA(RD) Address to /RD Low Setup 2. TdA(DR) Address to Read Data Valid TsCEI(WR) /CE ...
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Figure 4. Z80A CPU to Z8500 Peripheral Minimum I/O Cycle Timing UM010901-0601 ® Interfacing Z80 CPUs to the Z8500 Peripheral Family Application Note 6 6-7 ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family Z80B CPU TO Z8500A PERIPHERALS No additional Wait states are necessary during I/O cycles, although Wait states can be inserted to compensate for any systems delays. Although the Z80B ...
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Worst Case 6. TsA(WR) Address to /WR Low Setup 1. TsA(RD) Address to /RD Low Setup 2. TdA(DR) Address to Read Data Valid TsCE1(WR) /CE Low to /WR Low Setup TsCE1(RD) /CE Low to /RD Low Setup 4. TwRD1 /RD ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family Z90H CPU TO Z8500 PERIPHERALS During an I/O Read cycle, there are three Z8500 parameters that must be satisfied. Depending upon the loading characteristics of the /RD signal, the ...
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Figure 6. Z80H CPU to Z8500 Peripheral Minimum I/O Cycle Timing UM010901-0601 ® Interfacing Z80 CPUs to the Z8500 Peripheral Family Application Note 6 6-11 ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family Z80H CPU TO Z8500A PERIPHERALS During an I/O Read cycle, there are three Z8500A parameters that must be satisfied. Depending upon the loading characteristics of the /RD signal, the ...
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Figure 7. Z80H CPU to Z8500A Peripheral Minimum I/O Cycle Timing UM010901-0601 ® Interfacing Z80 CPUs to the Z8500 Peripheral Family Application Note 6 6-13 ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family Z80H CPU TO Z8500A PERIPHERALS (Continued) Z80H Z8500A Parameter Equation TsD(Cf) 4TcC+TwCh-TdCr(A)-TdA(DR) /RS - delayed 2TcC+TwCh-TdRD(DR) 6-14 Figure 8. Delaying /RD or /WR Table 14. Parameter Equations Value Units ...
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INTERRUPT ACKNOWLEDGE CYCLES The primary timing differences between the Z80 CPUs and Z8500 peripherals occur in the Interrupt Acknowledge cycle. The Z8500 timing parameters that are significant during Interrupt Acknowledge cycles are listed in Table 16, while the Z80 parameters ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family EXTERNAL INTERFACE LOGIC (Continued) Figure 9. Z80A/Z80B CPU to Z8500/Z8500A Peripheral Interrupt Acknowledge Interface Logic During I/O and normal memory access cycles, the Shift registers remains cleared because the ...
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Figure 10. Z80A/Z80B CPU to Z8500/Z8500A Peripheral Interrupt Acknowledge Interface Timing Z8500/Z8500A Peripherals Figure 11 depicts logic that can be used in interfacing the Z80H CPU to the Z8500/Z8500A peripherals. This logic is the same as that shown in Figure ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family EXTERNAL INTERFACE LOGIC (Continued) Figure 11. Z80H to Z8500/Z8500A Peripheral Interrupt Acknowledge Interface Logic During RETI cycles, the IEO line from the Z8500 peripherals does not change state as ...
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Figure 12. Z80H CPU to Z8500 Peripheral Interrupt Acknowledge Interface Timing Figure 13. Z80H CPU to Z8500A Peripheral Interrupt Acknowledge Interface Timing UM010901-0601 ® Interfacing Z80 CPUs to the Z8500 Peripheral Family Application Note 6 6-19 ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family EXTERNAL INTERFACE LOGIC (Continued) Figure 14. Z80 and Z8500 Peripheral Interrupt Acknowledge Interface Logic 6-20 UM010901-0601 ...
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Figure 15. Z80 and Z8500 Peripheral Interrupt Acknowledge Interface Timing UM010901-0601 ® Interfacing Z80 CPUs to the Z8500 Peripheral Family Application Note 6 6-21 ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family SOFTWARE CONSIDERATIONS - POLLED OPERATION There are several options available for servicing interrupts on the Z8500 peripherals. Since the vector of IP registers can be read at any time, ...
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... Because the CIO can be used in a polled interrupt environment, the /INT pin is connected to the Figure 16. Z80 to Z8500 Simple System Mode 1 Interrupt or Non-Interrupt Structure Additional Information in Zilog Publications: The Z80 Family User’s Manual includes technical information on the Z80 CPU, DMA, PIO, CTC, and SIO. ...
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... The SCC is the ideal device for this purpose. Zilog’s SCC is the multi-protocol (@ 10 MHz) universal serial communication controller which supports most serial communication applications including Monosync, Bisync and SDLC at 2.5 Mbits/sec speeds. Further, the wide acceptance of this device by the market ensures “ ...
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Application Note The Z180™ Interfaced with the SCC at MHZ INTERFACES The following subsections explain the interfaces between the: Z180 and Memory Z180 and I/O Z180 and SCC Basic goals of this system design are: System clock ...
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Table 1. Z8018010 Timing Parameters for Opcode Fetch Cycle (Worst Case: Z180 10 MHz) No Symbol 1 tcyc 2 tCHW 3 tCLW 4 tcf 6 tAD 8 tMED1 9 tRDD1 11 tAH 12 tMED2 15 tDRS 16 tDRH 22 tWRD1 ...
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Application Note The Z180™ Interfaced with the SCC at MHZ EPROM INTERFACE During an Opcode fetch cycle, data sampling of the bus is on the rising PHI clock edge of T3 and on the falling edge of T3 during a ...
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With this scheme, you can get the highest performance with moderate cost. SRAM Write Cycle. During a Z180 memory write cycle, the Z180 write data is stable before the falling edge of /WR Ø Address /MREQ /WR ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued) A9 A18 A17 A16 A15 /RD /MREQ /WR * /RD to /OE Pin of 27C256 and 55257 /WR To /WE Pin of 55257 /USRRAM /IORQ A15 /USRROM 6-30 HCT138 ...
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FFFFFH S-RAM Image F8000H EP-ROM Image F0000H S-RAM Image 28000H /EP-ROM Image 20000H S-RAM Image 18000H EP-ROM Image 10000H 256K SRAM 08000H EP-ROM 27C256 00000H Figure 5. Physical Memory Address Map UM010901-0601 The Z180™ Interfaced with the SCC at MHZ ...
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Application Note The Z180™ Interfaced with the SCC at MHZ Z180 TO I/O INTERFACE The Z180 I/O read/write cycle is similar to the Z80 CPU if you clear the /IOC bit in the OMCR register to 0 (Figures 7 Ø ...
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Table 5. Z8018010 Timing Parameters for I/O Cycle (Worst Case) No Symbol 1 tcyc 2 tCHW 3 tCLW 4 tcf 6 tAD 9 tRDD1 11 tAH 13 tRDD2 15 tDRS 16 tDRH 21 tWDZ 22 tWRD1 23 tWDD 24 ...
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... CPU Hardware Interfacing The hardware interface has three basic groups of signals: Data bus, system control, and interrupt control. For more detailed signal information, refer to Zilog’s Technical Manuals, and Product Specifications for each device. Data Bus Signals D7-D0. Data bus (Bidirectional, tri-state). This bus transfers data between the Z180 and SCC ...
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Address /INTACK /CE /RD D7-D0 Write Cycle Timing Figure 11 illustrates the SCC Write cycle timing. All register addresses and /INTACK are stable throughout the cycle. The timing specification of the SCC requires that the Address /INTACK /CE /WR D7-D0 ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued) SCC Interrupt Operation Understanding SCC interrupt operations requires a basic knowledge of the Interrupt Pending (IP) and Interrupt Under Service (IUS) bits in relation to the daisy chain. The ...
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Interrupt Condition IP Set IEI High? INT Active /INTACK * IEI * /RD The SCC uses /INTACK (Interrupt Acknowledge) for recognition of an interrupt acknowledge cycle. This pin, used with /RD, allows the SCC to gate its interrupt vector onto ...
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Application Note The Z180™ Interfaced with the SCC at MHZ INPUT/OUTPUT CYCLES Although the SCC is a universal design, certain timing parameters differ from the Z180 timing. The following subsections discuss the I/O interface for the Z180 MPU and SCC. ...
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Table 8. Parameter Equations Worst Case (Without Delay Signals - No Wait State) SCC Z180 Parameters Equation TsA(RD) tcyc-tAD+tRDD1 TdA(DR) 3tcyc+tCHW+tcf-tAD-tDRS TdRDf(DR) 2tcyc+tCHW+tcf-tRDD1-tDRS TwRDI 2tcyc+tCHW+tcf-tDRS+tRDD2 TsA(WR) tcyc-tAD+tWRD1 TsDW(WR) tWDS TwWRI tWRP Z180 SCC Parameters Equation tDRS Address 3tcyc+tCHW-tAD-TdA(DR) RD 2tcyc+tCHW-tRDD1-TdRD(DR) ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued) /CSSCC /WR HCT74 D CK Ø /RD /RESET /MREQ /M1 4.7K Internal /WAIT Input This circuit works when [(Lower HCT164’s CLK If you are running your system slower than ...
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Table 10. 10 MHz SCC Timing Parameters for Interrupt Acknowledge Cycle No Symbol 13 TsIAi(RD) 14 ThIA(RD) 15 ThIA(PC) 38 TwRDA 39 TwRDA 40 TdRDA(DR) 41 TsIEI(RDA) 42 ThIEI(RDA) 43 TdIEI(IEO) Table 11. Z180 Timing Parameters Interrupt Acknowledge Cycles (Worst ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued Address 6 /IORQ /SCCSEL HC74 /Q HCT164 /CLR HCT164 CLK 10 ns max HCT164 Q0 HCT164 Q1 /RD (or, /WR) RD* Q1 *SCCSEL /SCCRD /[(RD* /Q1* SCCSEL) ...
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The primary chip in this logic is the Shift register (HCT164), which generates /INTACK, /SCCRD and /WAIT. During I/O and normal memory access cycles, the Shift Register (HCT164) remains cleared because the /M1 signal is inactive during the opcode fetch ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued) 6-44 Figure 16a. ELPD Circuit Implementation UM010901-0601 ...
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UM010901-0601 Figure 16b. ELPD Circuit Implementation Application Note The Z180™ Interfaced with the SCC at MHZ 7 6-45 ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued) System Checkout After completion of the board (PC board or wire wrapped board, etc.), the following methods verify that the board is working. Software Considerations Based on the previous ...
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Table 12. SCC Test Program – Interrupt for 180/SCC Application Board (Under Mode2 Interrupt register returns status info: ;* Bit D0: current /cts stat ;* D1set: /cts int received ;* .z800 ;Read in Z180 register names and *include ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued) Table 12. SCC Test Program – Interrupt for 180/SCC Application Board (Under Mode2 Interrupt) (Continued) ;external/status interrupt service routine ext_stat: ld a,10h out in and rra rra rra rra ...
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Table 13 shows a “macro” to enable the Z180 to use the Z80 Assembler, as well as register definitions. There is one good test to ensure proper function. Generate a data transfer between the Z180/SCC using the Z180 on- Table ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued) Table 13. Program Example – Z180 CPU Macro Instructions (Continued) bcr1l: equ 2eh bcr1h: equ 2fh dstat: equ 30h dmode: equ 31h dcntl: equ 32h ;System Control Registers il: ...
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Table 13. Program Example – Z180 CPU Macro Instructions (Continued) db 10000011B endm otimr macro db 11101101B db 10010011B endm otdm macro db 11101101B db 10001011B endm otdmr macro db 11101101B db 10011011B endm tstio macro ?p db 11101101B db ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued) Table 14 lists a program example for the Z180/SCC DMA transfer test. Table 14. Test Program – Z180/SCC DMA Transfer ; ;* Test program for 180 DMA/SCC ;* ;* ...
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Table 14. Test Program – Z180/SCC DMA Transfer (Continued) loop: chkloop: ld bad_data: good: enddma: ; fill_mem: l fill_loop: fill_00: fill_00l: UM010901-0601 call initdma ld b,0 ld a,00h out (scc_data),a ld a,11001100b out0 (dstat),a ld a,05h out (scc_cont),a ld a,01101000b ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued) Table 14. Test Program – Z180/SCC DMA Transfer (Continued) initscc: init0: ;initialize z180’s scc ; initdma: txend: rxend: ;initialization data table for scc ;table format - register number, then ...
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Table 14. Test Program – Z180/SCC DMA Transfer (Continued) UM010901-0601 db 01h db 01100000b db 02h db 00h db 03h db 11000000b db 05h db 01100000b db 06h db 00h db 07h db 00h db 09h db 00000001b db 0ah ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued) Table 14. Test Program – Z180/SCC DMA Transfer (Continued) ;source/dist addr table for Z180’s dma addrtab: ;interrupt vector table z180vect: tx_buff: rx_buff: temp: end 6-56 db 01h db 11100000b ...
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... This program example specifies a way to initialize the SCC and the Z180 DMA. For further design assistance, a completed board together with the Debug/Monitor program and the listed sample program are available. If interested, please contact your local Zilog sales office. Application Note 7 6-57 ...
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... Intel environment. INTRODUCTION Zilog’s customers need a way to evaluate its serial communications controllers with a central CPU. This App Note (Application Note) explains and illustrates how the datacom family interfaces and communicates with the 80186 on this evaluation board ...
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... Table 2. Counter/Timer Signal Locations J26 pin The 80186’s integrated interrupt controller is largely bypassed in favor of the traditional Zilogical interrupt daisy-chain structure. Install this jumper: J23-1 to J23-2 J22-1 to J22-2 J22-4 to J22-2 J29-1 to J29-2 J29-4 to J29-2 Install this Jumper: J24-1 to J24-3 ...
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... In particular, the UMCS register (address A0H within the 80186’s Peripheral Control Block) UM010901-0601 The Zilog Datacom Family with the 80186 CPU addresses of the datacom controllers are programmed in the 80186 for the /PCS6-/PCS0 outputs block of 128x7=896 bytes starting Kbyte boundary. The block can be in I/O space part of memory space that is not used for SRAM or EPROM ...
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... Application Note The Zilog Datacom Family with the 80186 CPU RAM Six 32-pin sockets are provided; they should be populated in pairs, starting with the lower-numbered sockets, to allow for 16-bit accesses provided at both pin 32 and pin that 28-pin 32K x 8 SRAMs can be installed in pins ...
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... This variability is provided in part because early versions of the 85230 ESCC had trouble passing an interrupt acknowledge down the daisy chain if it occurred in UM010901-0601 The Zilog Datacom Family with the 80186 CPU Table 6. Address Ranges for Reset Address Range for which ISCC, MMCS value ...
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... Application Note The Zilog Datacom Family with the 80186 CPU (E)SCC Socket U2 can be configured for either an ESCC or SCC, and for versions thereof that use either multiplexed or non- multiplexed address and data. Jumper blocks J20 and J21 select certain signals accordingly. For a part with ...
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... A/B selection is taken from A5 of the multiplexed address.) UM010901-0601 The Zilog Datacom Family with the 80186 CPU basic (E)SCC register map occurs twice in the even addresses from (PBA) through (PBA)+126: Channel B registers 0-15 ...