Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 11

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

CMOS SCC Serial Communications Controller
Product Specification
7
DTR/REQA, DTR/REQB
These outputs follow the state
Data Terminal Ready/Request (outputs, active Low) —
programmed into the
bit. They can also be used as general-purpose outputs or as
DTR
Request lines for a DMA controller.
IEI
IEI is used with IEO to form an interrupt
Interrupt Enable In (input, active High) —
daisy-chain when there is more than one interrupt driven device. A high IEI indicates that
no other higher priority device has an interrupt under service or is requesting an interrupt.
IEO
IEO is High only if IEI is High and the
Interrupt Enable Out (output, active High) —
CPU is not servicing the SCC interrupt or the SCC is not requesting an interrupt (interrupt
Acknowledge cycle only). IEO is connected to the next lower priority device’s IEI input
and thus inhibits interrupts from lower priority devices.
INT
This signal activates when the
Interrupt Request (output, open-drain, active Low) —
SCC requests an interrupt.
INTACK
This signal indicates an active Interrupt
Interrupt Acknowledge (input, active Low) —
Acknowledge cycle. During this cycle, the SCC interrupt daisy chain settles. When RD is
active, the SCC places an interrupt vector on the data bus (if IEI is High). INTACK is
latched by the rising edge of PCLK.
PCLK
This is the master SCC clock used to synchronize internal signals. PCLK
Clock (input) —
is a TTL level signal. PCLK is not required to have any phase relationship with the master
system clock. The maximum transmit rate is 1/4 PCLK.
RxDA, RxDB
These signals receive serial data at standard TTL
Receive Data (inputs, active High) —
levels.
RTxCA, RTxCB
These pins can be programmed in
Receive/Transmit Clocks (inputs, active Low) —
several different operating modes. In each channel, RTxC can supply the receive clock, the
transmit clock, clock for the Baud Rate Generator, or the clock for the Digital Phase-
Locked Loop. These pins can also be programmed for use with the respective SYNC pins
as a crystal oscillator. The receive clock can be 1, 16, 32, or 64 times the data rate in Asyn-
chronous modes.
PS011705-0608
General Description