Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 12

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

CMOS SCC Serial Communications Controller
Product Specification
8
RTSA, RTSB
When the Request To Send (RTS) bit in
Request To Send (outputs, active Low) —
Write Register 5 (see
Figure 9
on page 19) is set, the RTS signal goes Low. When the RTS
bit is reset in the Asynchronous mode and Auto Enable is ON, the signal goes High after
the transmitter is empty. In Synchronous mode, it strictly follows the state of the RTS bit.
When Auto Enable is OFF, the RTS pins can be used as general-purpose outputs.
SYNCA, SYNCB
These pins function as inputs,
Synchronization (inputs or outputs, active Low) —
outputs, or part of the crystal oscillator circuit. In the Asynchronous Receive mode (crystal
oscillator option not selected), these pins are inputs similar to CTS and DCD. In this
mode, transitions on these lines affect the state of the Synchronous/Hunt status bits in
Read Register 0 (see
Figure 8
on page 17) but have no other function.
In External Synchronization mode with the crystal oscillator not selected, these lines also
act as inputs. In this mode, SYNC must be driven Low for two receive clock cycles after
the last bit in the synchronous character is received. Character assembly begins on the
rising edge of the receive clock immediately preceding the activation of SYNC.
In the Internal Synchronization mode (Monosync and Bisync) with the crystal oscillator
not selected, these pins act as outputs and are active only during the part of the receive
clock cycle in which synchronous characters are recognized. This synchronous condition
is not latched. These outputs are active each time a synchronization pattern is recognized
(regardless of character boundaries). In SDLC mode, these pins act as outputs and are
valid on receipt of a flag.
TxDA, TxDB
These output signals transmit serial data at
Transmit Data (outputs, active High) —
standard TTL levels.
TRxCA, TRxCB
These pins can be
Transmit/Receive Clocks (inputs or outputs, active Low) —
programmed in several different operating modes. TRxC may supply the receive clock or
the transmit clock in the input mode or supply the output of the Digital Phase-locked loop,
the crystal oscillator, the Baud Rate Generator, or the transmit clock in the output mode.
W/REQA, W/REQB
Wait/Request (outputs, open-drain when programmed for a Wait function, driven
These dual-purpose outputs
High or low when programmed for a Request function) —
can be programmed as Request lines for a DMA controller or as Wait lines to synchronize
the CPU to the SCC data rate. The reset state is Wait.
PS011705-0608
General Description