Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 24

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

CMOS SCC Serial Communications Controller
Product Specification
20
Asynchronous Modes
Send and Receive is accomplished independently on each channel with five to eight bits
per character, plus optional even or odd parity. The transmitters can supply one, one-and-
a-half, or two stop bits per character and can provide a break output at any time. The
receiver break-detection logic interrupts the CPU both at the start and at the end of a
received break.
Reception is protected from spikes by a transient spike-rejection mechanism that checks
the signal one-half a bit time after a Low level is detected on the receive data input (RxDA
or RxDB pins). If the Low does not persist (a transient), the character assembly process
does not start.
Framing errors and overrun errors are detected and buffered together with the partial char-
acter on which they occur. Vectored interrupts allow fast servicing or error conditions
using dedicated routines. A built-in checking process avoids the interpretation of a fram-
ing error as a new start bit. A framing error results in the addition of one-half a bit time to
the point at which the search for the next start bit begins.
The SCC does not require symmetric transmit and receive clock signals - a feature allow-
ing use of the wide variety of clock sources. The transmitter and receiver handle data at a
rate supplied to the receive and transmit clock inputs. In Asynchronous modes, the SYNC
pin can be programmed as an input used for functions such as monitoring a ring indicator.
Synchronous Modes
The SCC supports both byte and bit-oriented synchronous communication. Synchronous
byte-oriented protocols are handled in several modes. They allow character synchroniza-
tion with a 6-bit or 8-bit sync character (Monosync), and a 12-bit or 16-bit synchroniza-
tion pattern (Bisync), or with an external sync signal. Leading sync characters are
removed without interrupting the CPU.
5- or 7-bit synchronous characters are detected with 8- or 16-bit patterns in the SCC by
overlapping the larger pattern across multiple incoming synchronous characters as
displayed in
Figure
10.
7 Bits
SYNC
Data
Data
Data
SYNC
SYNC
Data
8
16
Figure 10. Detecting 5- or 7-Bit Synchronous Characters
CRC checking for Synchronous byte-oriented modes is delayed by one character time so
that the CPU can disable CRC checking on specific characters. This feature permits the
implementation of protocols such as IBM Bisync.
PS011705-0608
Functional Description