Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 27

IC 10MHZ Z8500 CMOS SCC 40-DIP

Z85C3010PSG

Manufacturer Part Number
Z85C3010PSG
Description
IC 10MHZ Z8500 CMOS SCC 40-DIP
Manufacturer
Zilog
Series
SCCr
Datasheets

Specifications of Z85C3010PSG

Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Cpu Speed
8MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3934
Z85C3010PSG

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CMOS SCC Serial Communications Controller
Product Specification
23
Baud Rate Generator
Each channel in the SCC contains a programmable Baud Rate Generator (BRG). Each
generator consists of two 8-bit time constant registers that form a 16-bit time constant, a
16-bit down counter, and a flip-flop on the output producing a square wave. On startup,
the output flip-flop is set in a High state, the value in the time constant register is loaded
into the counter, and the counter starts counting down. The output of the BRG toggles
when reaching 0, the value in the time constant register is loaded into the counter, and the
process is repeated. The time constant can be changed at any time, but the new value does
not take effect until the next load of the counter.
The output of the BRG can be used as either the transmit clock, the receive clock, or both.
It can also drive the Digital Phase-locked loop (see
Digital Phase-Locked
Loop).
If the receive clock or transmit clock is not programmed to come from the TRxC pin, the
output of the BRG can be echoed out through the TRxC pin. The following formula relates
the time constant to the baud rate where PCLK or RTxC is the BRG input frequency in
Hertz. The clock mode is 1, 16, 32, or 64, as selected in Write Register 4, bits D6 and D7.
Synchronous operation modes select 1 and Asynchronous modes select 16, 32 or 64.
PCLK or RTxC Frequency
-2
Time Constant =
2(Baud Rate)(Clock Mode)
Digital Phase-Locked Loop
The SCC contains a Digital Phase-Locked Loop (DPLL) to recover clock information
from a data stream with NRZI or FM encoding. The DPLL is driven by a clock that is
nominally 32 (NRZI) or 16 (FM) times the data rate. The DPLL uses this clock, along with
the data stream, to construct a clock for the data. This clock is used as the SCC receive
clock, the transmit clock, or both. When the DPLL is selected as the transmit clock source,
it provides a jitter-free clock output that is the DPLL input frequency divided by the
appropriate divisor for the selected encoding technique.
For NRZI encoding, the DPLL counts the 32x clock to create nominal bit times. As the
32x clock is counted, the DPLL is searching the incoming data stream for edges (either 1
to 0, or 0 to 1). Whenever an edge is detected, the DPLL makes a count adjustment (during
the next counting cycle), producing a terminal count closer to the center of the bit cell.
For FM encoding, the DPLL again counts from 0 to 31, but with a cycle corresponding to
two bit times. When the DPLL is locked, the clock edges in the data stream occur between
counts 15 and 16 and between counts 31 and 0. The DPLL looks for edges only during a
time centered on the 15 to 16 counting transition.
The 32x clock for the DPLL can be programmed to come from either the RTxC input or
the output of the BRG. The DPLL output can be programmed to be echoed out of the SCC
through the TRxC pin (if this pin is not being used as an input).
PS011705-0608
Functional Description

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