Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 6

IC 10MHZ Z8500 CMOS SCC 40-DIP

Z85C3010PSG

Manufacturer Part Number
Z85C3010PSG
Description
IC 10MHZ Z8500 CMOS SCC 40-DIP
Manufacturer
Zilog
Series
SCCr
Datasheets

Specifications of Z85C3010PSG

Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Cpu Speed
8MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3934
Z85C3010PSG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z85C3010PSG
Manufacturer:
Zilog
Quantity:
135
Part Number:
Z85C3010PSG
Manufacturer:
Zilog
Quantity:
326
Part Number:
Z85C3010PSG
Quantity:
1 994
Other Features for Z85C30 Only
PS011705-0608
Some of the features listed below are available by default. Some of them (features with
*) are disabled on default to maintain compatibility with the existing Serial
Communications Controller (SCC) design, and “program to enable through WR7”:
New programmable WR7 (Write register 7 prime) to enable new features.
Improvements to support SDLC mode of synchronous communication:
Improved AC timing:
Other features include:
Improve functionality to ease sending back-to-back frames.
Automatic SDLC opening Flag transmission.*
Automatic Tx Underrun/EOM Latch reset in SDLC mode.*
Automatic RTS deactivation.*
TxD pin forced High in SDLC NRZI mode after closing flag.*
Complete CRC reception.*
Improved response to Abort sequence in status FIFO.
Automatic Tx CRC generator preset/reset.
Extended Read for Write registers.*
Write data set-up timing improvement.
3 to 3.6 PCLK access recovery time.
Programmable DTR/REQ timing.*
Write data to falling edge of WR setup time requirement is now eliminated.
Reduced INT timing.
Extended Read function to read back the written value to the Write registers.*
Latching RRO during read.
RRO, bit D7 and RR10, bit D6 now has reset default value.
CMOS SCC Serial Communications Controller
Product Specification
Overview
2

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