IC WEBSERVER 50MHZ 100LQFP

EZ80L92AZ050SG

Manufacturer Part NumberEZ80L92AZ050SG
DescriptionIC WEBSERVER 50MHZ 100LQFP
ManufacturerZilog
EZ80L92AZ050SG datasheet
 


Specifications of EZ80L92AZ050SG

Processor TypeeZ80FeaturesHigh Speed, Single-Cycle Instruction-Fetch
Speed50MHzVoltage3.3V
Mounting TypeSurface MountPackage / Case100-LQFP
Processor SeriesEZ80L92xCoreeZ80
Data Bus Width8 bitProgram Memory Size64 KB
Interface TypeI2C, SPI, UARTMaximum Clock Frequency50 MHz
Number Of Programmable I/os24Number Of Timers6
Operating Supply Voltage3 V to 3.6 VMaximum Operating Temperature+ 70 C
Mounting StyleSMD/SMTDevelopment Tools By SuppliereZ80L920210ZCO
Minimum Operating Temperature0 CLead Free Status / RoHS StatusLead free / RoHS Compliant
Other names269-3878
EZ80L92AZ050SG
  
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eZ80Acclaim!
Flash Microcontrollers
eZ80L92 MCU
Product Specification
PS013014-0107
Copyright ©2007 by ZiLOG, Inc. All rights reserved.
www.zilog.com

EZ80L92AZ050SG Summary of contents

  • Page 1

    ... Flash Microcontrollers eZ80L92 MCU Product Specification PS013014-0107 Copyright ©2007 by ZiLOG, Inc. All rights reserved. www.zilog.com ...

  • Page 2

    ... No licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights. ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. eZ80Acclaim!, eZ80, and Z80 are trademarks or registered trademarks of ZiLOG Inc. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated ...

  • Page 3

    ... Clock Rise to CSx De-assertion Delay (Figure 50). Real Time Clock Clarified language Oscillator and Source describing RTC drive Selection frequency. Revisions to BGR Divisor, UART text Modified to remove "zservice@zilog.com" and other external hyperlinks. eZ80L92 MCU Product Specification iii Page No 113 All All 82 205 ...

  • Page 4

    Table of Contents Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 5

    ... C Serial I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Transferring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 ZiLOG Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 ZDI-Supported Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 ZDI Clock and Data Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 ZDI Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 ZDI Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 ZDI Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 ZDI Read Operations ...

  • Page 6

    ZDI Read-Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 7

    ... Architectural Overview ZiLOG’s eZ80L92 MCU is a high-speed single-cycle instruction-fetch microcontroller with a maximum clock speed of 50 MHz. The eZ80L92 MCU is a member of ® eZ80Acclaim! addressing mode (64 KB) or full 24-bit addressing mode (16 MB). The rich peripheral set of the eZ80L92 MCU makes it suitable for various applications including industrial control, embedded communication, and point-of-sale terminals ...

  • Page 8

    Operating temperature range: Standard, 0 ºC to +70 ºC – Extended, –40 ºC to +105 ºC – Note: All signals with an overline are active Low. For example, B/W, for which WORD is active Low, and B/W, for which ...

  • Page 9

    ... RTS0/1 RxD0/1 TxD0/1 IrDA Encoder/ Decoder PS013014-0107 Real-Time RTC_V Clock and RTC_X 32 KHz RTC_X Oscillator Bus Controller eZ80 CPU ZiLOG Debug Interface (JTAG/ZDI) Interrupt Vector [7:0] Interrupt Controller 8-Bit Crystal Programmable General Oscillator Purpose and Timer/Counters I/O Port System Clock ...

  • Page 10

    Pin Description Figure 2 illustrates the pin layout of the eZ80L92 MCU in the 100-pin LQFP package. Table 1 lists the 100-Pin LQFP pins and their functions. ADDR0 1 ADDR1 2 ADDR2 3 ADDR3 4 ADDR4 5 ADDR5 6 V ...

  • Page 11

    Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU Pin No Symbol Function 1 ADDR0 Address Bus 2 ADDR1 Address Bus 3 ADDR2 Address Bus 4 ADDR3 Address Bus 5 ADDR4 Address Bus 6 ADDR5 Address Bus PS013014-0107 Signal Direction ...

  • Page 12

    Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued) Pin No Symbol Function 7 V Power Supply Ground SS 9 ADDR6 Address Bus 10 ADDR7 Address Bus 11 ADDR8 Address Bus 12 ADDR9 Address Bus 13 ...

  • Page 13

    Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued) Pin No Symbol Function 14 ADDR11 Address Bus 15 ADDR12 Address Bus 16 ADDR13 Address Bus 17 ADDR14 Address Bus 18 V Power Supply Ground SS 20 ...

  • Page 14

    Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued) Pin No Symbol Function 21 ADDR16 Address Bus 22 ADDR17 Address Bus 23 ADDR18 Address Bus 24 ADDR19 Address Bus 25 ADDR20 Address Bus PS013014-0107 Signal Direction Description Bidirectional Configured ...

  • Page 15

    Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued) Pin No Symbol Function 26 ADDR21 Address Bus 27 ADDR22 Address Bus 28 ADDR23 Address Bus 29 CS0 Chip Select 0 30 CS1 Chip Select 1 31 CS2 Chip Select ...

  • Page 16

    Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued) Pin No Symbol Function 35 DATA0 Data Bus 36 DATA1 Data Bus 37 DATA2 Data Bus 38 DATA3 Data Bus 39 DATA4 Data Bus 40 DATA5 Data Bus 41 DATA6 ...

  • Page 17

    Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued) Pin No Symbol Function 43 V Power Supply Ground SS 45 IORQ Input/Output Request 46 MREQ Memory Request 47 RD Read 48 WR Write 49 INSTRD Instruction ...

  • Page 18

    Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued) Pin No Symbol Function 52 NMI Nonmaskable Interrupt 53 BUSREQ Bus Request 54 BUSACK Bus Acknowledge 55 HALT_SLP HALT and SLEEP Indicator 56 V Power Supply Ground ...

  • Page 19

    Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued) Pin No Symbol Function 63 TCK JTAG Test Clock 64 TRIGOUT JTAG Test Trigger Output 65 TDI JTAG Test Data In 66 TDO JTAG Test Data Out 67 V Power ...

  • Page 20

    Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued) Pin No Symbol Function 70 PD2 GPIO Port D RTS0 Request to Send 71 PD3 GPIO Port D CTS0 Clear to Send 72 PD4 GPIO Port D DTR0 Data Terminal ...

  • Page 21

    Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued) Pin No Symbol Function 74 PD6 GPIO Port D DCD0 Data Carrier Detect 75 PD7 GPIO Port D RI0 Ring Indicator Input, Active Low 76 PC0 GPIO Port C TxD1 ...

  • Page 22

    Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued) Pin No Symbol Function 77 PC1 GPIO Port C RxD1 Receive Data 78 PC2 GPIO Port C RTS1 Request to Send 79 PC3 GPIO Port C CTS1 Clear to Send ...

  • Page 23

    Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued) Pin No Symbol Function 80 PC4 GPIO Port C DTR1 Data Terminal Ready 81 PC5 GPIO Port C DSR1 Data Set Ready 82 PC6 GPIO Port C DCD1 Data Carrier ...

  • Page 24

    Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued) Pin No Symbol Function 84 V Ground System Clock IN Oscillator Input 86 X System Clock OUT Oscillator Output 87 V Power Supply DD 88 PB0 GPIO ...

  • Page 25

    Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued) Pin No Symbol Function 90 PB2 GPIO Port B SS Slave Select 91 PB3 GPIO Port B SCK SPI Serial Clock 92 PB4 GPIO Port B T4_OUT Timer 4 Out ...

  • Page 26

    Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued) Pin No Symbol Function 94 PB6 GPIO Port B MISO Master In Slave Out 95 PB7 GPIO Port B MOSI Master Out Slave Power Supply DD 97 ...

  • Page 27

    Pin Characteristics Table 2 describes the characteristics of each pin in the package. Table 2. Pin Characteristics of eZ80L92 MCU Pin No. Symbol Direction 1 ADDR0 I/O 2 ADDR1 I/O 3 ADDR2 I/O 4 ADDR3 I/O 5 ADDR4 I/O 6 ...

  • Page 28

    Table 2. Pin Characteristics of eZ80L92 MCU (Continued) Pin No. Symbol Direction 25 ADDR20 I/O 26 ADDR21 I/O 27 ADDR22 I/O 28 ADDR23 I/O 29 CS0 O 30 CS1 O 31 CS2 O 32 CS3 ...

  • Page 29

    Table 2. Pin Characteristics of eZ80L92 MCU (Continued) Pin No. Symbol Direction 53 BUSREQ I 54 BUSACK O 55 HALT_SLP RTC_X RTC_X I/O OUT V 60 RTC_ DD 61 ...

  • Page 30

    Table 2. Pin Characteristics of eZ80L92 MCU (Continued) Pin No. Symbol Direction 80 PC4 I/O 81 PC5 I/O 82 PC6 I/O 83 PC7 I OUT PB0 ...

  • Page 31

    Register Map All on-chip peripheral registers are accessed in the I/O address space. All I/O operations employ 16-bit addresses. The upper byte of the 24-bit address bus is undefined during all I/O operations (ADDR[23:16] = range – 0080h 00FFh not ...

  • Page 32

    Table 3. Register Map (Continued) Address (hex) Mnemonic Name 0089 TMR3_CTL Timer 3 Control Register 008A TMR3_DR_L Timer 3 Data Register—Low Byte TMR3_RR_L Timer 3 Reload Register—Low Byte 008B TMR3_DR_H Timer 3 Data Register—High Byte TMR3_RR_H Timer 3 Reload Register—High ...

  • Page 33

    Table 3. Register Map (Continued) Address (hex) Mnemonic Name 00A3 PD_DDR Port D Data Direction Register 00A4 PD_ALT1 Port D Alternate Register 1 00A5 PD_ALT2 Port D Alternate Register 2 Chip Select/Wait State Generator 00A8 CS0_LBR Chip Select 0 Lower ...

  • Page 34

    Table 3. Register Map (Continued) Address (hex) Mnemonic Name Universal Asynchronous Receiver/Transmitter 0 (UART0) Block 00C0 UART0_RBR UART 0 Receive Buffer Register UART0_THR UART 0 Transmit Holding Register UART0_BRG_L UART 0 Baud Rate Generator Register—Low Byte 00C1 UART0_IER UART 0 ...

  • Page 35

    Table 3. Register Map (Continued) Address (hex) Mnemonic Name Universal Asynchronous Receiver/Transmitter 1 (UART1) Block 00D0 UART1_RBR UART 1 Receive Buffer Register UART1_THR UART 1 Transmit Holding Register UART1_BRG_L UART 1 Baud Rate Generator Register—Low Byte 00D1 UART1_IER UART 1 ...

  • Page 36

    Table 3. Register Map (Continued) Address (hex) Mnemonic Name 00E9 RTC_AMIN RTC Alarm Minutes Register 00EA RTC_AHRS RTC Alarm Hours Register 00EB RTC_ADOW RTC Alarm Day-of-the-Week Register 00EC RTC_ACTRL RTC Alarm Control Register 00ED RTC_CTRL RTC Control Register Chip Select ...

  • Page 37

    ... CPU Core ® ® ZiLOG’s eZ80 Each software module or task under a real-time executive or operating system can operate in Z80 compatible (64 KB) mode or full 24-bit (16 MB) address mode. The eZ80 CPU instruction set is a superset of the instruction sets for the Z80 and Z180 CPUs ...

  • Page 38

    Four other block transfer instructions are modified to improve performance related to the eZ80190 device. These modified instructions are: IND2R (input from I/O, decrement the memory address, decrement the I/O – address, and repeat). INI2R (input from I/O, increment ...

  • Page 39

    Reset RESET Operation The RESET controller within the eZ80L92 MCU provides a consistent system reset (RESET) function for all type of resets that may affect the system. Following four events can cause a RESET: • External RESET pin assertion. • ...

  • Page 40

    Low-Power Modes The eZ80L92 MCU provides a range of power-saving features. The highest level of power reduction is provided by SLEEP mode. The next level of power reduction is provided by the HALT instruction. The lowest level of power reduction ...

  • Page 41

    The eZ80 CPU can be brought out of HALT mode by any of the following operations: • Non-maskable interrupt (NMI). • Maskable interrupt. • RESET through the external RESET pin driven Low. • Watchdog Timer time-out (if configured to generate ...

  • Page 42

    Table 4. Clock Peripheral Power-Down Register 1 (CLK_PPD1 = 00DBh) Bit Reset CPU Access Note: R/W = Read/Write Read Only. Bit Position 7 GPIO_D_OFF 6 GPIO_C_OFF 5 GPIO_B_OFF 4 3 SPI_OFF 2 I2C_OFF 1 UART1_OFF 0 UART0_OFF PS013014-0107 ...

  • Page 43

    Table 5. Clock Peripheral Power-Down Register 2 (CLK_PPD2 = 00DCh) Bit Reset CPU Access Note: R/W = Read/Write Read Only. Bit Position 7 PHI_OFF 6 5 PRT5_OFF 4 PRT4_OFF 3 PRT3_OFF 2 PRT2_OFF 1 PRT1_OFF 0 PRT0_OFF PS013014-0107 ...

  • Page 44

    General-Purpose Input/Output The eZ80L92 MCU features 24 General-Purpose Input/Output (GPIO) pins. The GPIO pins are assembled as three 8-bit ports — Port B, Port C, and Port D. All port signals can be configured for use as either inputs or ...

  • Page 45

    Table 6. GPIO Mode Selection GPIO Px_ALT2 Px_ALT1 Px_DDR Mode Bits7:0 Bits7 ...

  • Page 46

    Writing the Port x Data register outputs a High at the pin. Writing the Port x Data register results in a high-impedance output. Reserved. This pin generates high-impedance output. GPIO Mode 5. This bit ...

  • Page 47

    Data Bus System Clock GPIO Register Data (Output) GPIO Interrupts Each port pin can be used as an interrupt source. Interrupts are either level-triggered or edge-triggered. Level-Triggered Interrupts When the port is configured for level-triggered interrupts, the corresponding port pin ...

  • Page 48

    Port x Data register causes a reset of the edge-detected interrupt. You must set the bit in the Port x Data register to 1 before entering either single or dual edge-triggered interrupt ...

  • Page 49

    Port x Data Direction Registers In addition to the other GPIO Control Registers, the Port x Data Direction Registers (see Table 8) control the operating modes of the GPIO port pins. See Table 8. Port x Data Direction Registers (PB_DDR ...

  • Page 50

    Interrupt Controller The interrupt controller on the eZ80L92 MCU routes the interrupt request signals from the internal peripherals and external devices (through the GPIO pins) to the eZ80 CPU. Maskable Interrupts On the eZ80L92 MCU, all maskable interrupts use the ...

  • Page 51

    I[7:0], 1Eh} and {MBASE, I[7:0], 1Fh}. The least significant byte is stored at the lower address. When any one or more of the interrupt requests (IRQs) become active, an interrupt request is generated by the interrupt controller and sent ...

  • Page 52

    Table 12. Vectored Interrupt Operation (Continued) Memory ADL MADL Mode Bit Bit Operation ADL Mode 1 0 Read the LSB of the interrupt vector placed on the internal vectored interrupt bus, IVECT [7:0], by the interrupting peripheral. • IEF1 ← ...

  • Page 53

    Table 12. Vectored Interrupt Operation (Continued) Memory ADL MADL Mode Bit Bit Operation ADL Mode 1 1 Read the LSB of the interrupt vector placed on the internal vectored interrupt bus, IVECT [7:0], by the interrupting peripheral. • IEF1 • ...

  • Page 54

    Chip Selects and Wait States The eZ80L92 MCU generates four Chip Selects for external devices. Each Chip Select is programmed to access either memory space or I/O space. The Memory Chip Selects can be individually programmed ...

  • Page 55

    Memory Chip Select Priority A lower-numbered Chip Select is given priority over a higher-numbered Chip Select. For example, if the address space of Chip Select 0 overlaps the Chip Select 1 address space, Chip Select 0 is active. RESET States ...

  • Page 56

    Table 13. Register Values for Memory Chip Select Example in Figure 4 Chip CSx_CTL[3] CSx_CTL[4] Select CSx_EN CSx_IO CS0 1 0 CS1 1 0 CS2 1 0 CS3 1 0 I/O Chip Select Operation I/O Chip Selects are active when ...

  • Page 57

    If all the above conditions are met to generate an I/O Chip Select, then the following actions occur: • The appropriate Chip Select—CS0, CS1, CS2, or CS3—is asserted (driven Low). • IORQ is asserted (driven Low). • Depending upon the ...

  • Page 58

    An example of WAIT state operation is illustrated in Select is configured to provide a single WAIT state. The external peripheral being accessed drives the WAIT pin Low to request assertion of an additional WAIT state. If the WAIT pin ...

  • Page 59

    Chip Selects During Bus Request/Bus Acknowledge Cycles When the CPU relinquishes the address bus to an external peripheral in response to an external bus request (BUSREQ), it drives the bus acknowledge pin (BUSACK) Low. The external peripheral then drives the ...

  • Page 60

    During Write operations, Z80 Bus Mode employs 3 states (T1, T2, and T3) as described in Table 15. ® Table 15. Z80 Bus Mode Write States STATE T1 The Write cycle begins in State T1. The CPU drives the address ...

  • Page 61

    System Clock ADDR[23:0] DATA[7:0] CSx RD WAIT WR MREQ or IORQ PS013014-0107 CLK ® Figure 7. Z80 Bus Mode Read Timing Example eZ80L92 MCU Product Specification T3 Chip Selects and Wait States 55 ...

  • Page 62

    System Clock ADDR[23:0] DATA[7:0] CSx RD WAIT WR MREQ or IORQ Intel Bus Mode Chip selects configured for Intel Bus Mode modify the eZ80 bus signals to duplicate a four-state memory transfer similar to that found on Intel-style microprocessors. The ...

  • Page 63

    Bus Mode Signals (Pins) INSTRD RD WR WAIT MREQ IORQ ADDR[23:0] DATA[7:0] Intel Bus Mode (Separate Address and Data Buses) During Read operations with separate address and data buses, the Intel Bus Mode employs 4 states (T1, T2, T3, ...

  • Page 64

    Table 16. Intel (Continued) STATE T3 During State T3, no bus signals are altered. If the external ReadY (WAIT) pin is driven Low at least one eZ80 system clock cycle prior to the beginning of State T3, additional WAIT ...

  • Page 65

    System Clock ADDR[23:0] DATA[7:0] CSx ALE RD READY WR MREQ or IORQ ® Figure 10. Intel Bus Mode Read Timing Example (Separate Address and Data Buses) PS013014-0107 WAIT eZ80L92 MCU Product Specification 59 T4 Chip Selects ...

  • Page 66

    Clock DR[23:0] DATA[7:0] CSx ALE WR READY RD MREQ or IORQ ® Figure 11. Intel Bus Mode Write Timing Example (Separate Address and Data Buses) PS013014-0107 WAIT eZ80L92 MCU Product Specification T4 Chip Selects and ...

  • Page 67

    Intel Bus Mode (Multiplexed Address and Data Bus) During Read operations with multiplexed address and data, the Intel 4 states (T1, T2, T3, and T4) as described in ® Table 18. Intel STATE T1 The Read cycle begins in ...

  • Page 68

    Signal timing for Intel Read operation in ® Intel Bus Mode state is 2 eZ80 system clock cycles in duration. also illustrate the assertion of one WAIT state ( System Clock ADDR[23:0] DATA[7:0] CSx ALE RD READY WR MREQ or ...

  • Page 69

    System Clock ADDR[23:0] DATA[7:0] CSx ALE WR READY RD MREQ or IORQ ® Figure 13. Intel Bus Mode Write Timing Example (Multiplexed Address and Data Bus) Motorola Bus Mode Chip selects configured for Motorola Bus Mode modify the eZ80 bus ...

  • Page 70

    Bus Mode Signals (Pins) INSTRD RD WR WAIT MREQ IORQ ADDR[23:0] DATA[7:0] Figure 14. Motorola Bus Mode Signal and Pin Mapping During Write operations, the Motorola Bus Mode employs 8 states (S0, S1, S2, S3, S4, S5, S6, and ...

  • Page 71

    Table 20. Motorola Bus Mode Read States (Continued) STATE S6 During state S6, data from the external peripheral device is driven onto the data bus. STATE S7 On the rising edge of the clock entering state S7, the CPU latches ...

  • Page 72

    S0 System Clock ADDR[23:0] DATA[7:0] CSx AS DS R/W DTACK MREQ or IORQ Figure 15. Motorola Bus Mode Read Timing Example PS013014-0107 eZ80L92 MCU Product Specification Chip Selects and Wait States ...

  • Page 73

    S0 System Clock ADDR[23:0] DATA[7:0] CSx AS DS R/W DTACK MREQ or IORQ Figure 16. Motorola Bus Mode Write Timing Example Switching Between Bus Modes Each time the bus mode controller must switch from one bus mode to another, there ...

  • Page 74

    For I/O Chip Selects, this register defines the address to which ADDR[15:8] is compared to generate an I/O Chip Select. All Chip Select lower bound registers reset to Table 22. Chip Select x Lower Bound Registers ...

  • Page 75

    Chip Select x Upper Bound Registers For Memory Chip Selects, the Chip Select x Upper Bound registers, detailed in defines the upper bound of the address range for which the corresponding Chip Select (if enabled) can be active. For I/O ...

  • Page 76

    Chip Select x Control Registers The Chip Select x Control register, detailed in the type of Chip Select, and sets the number of WAIT states. The reset state for the Chip Select 0 Control register is registers is . 00h ...

  • Page 77

    Chip Select x Bus Mode Control Registers The Chip Select Bus Mode register, detailed in ® eZ80, Z80, Intel to interface to peripherals based on the Z80, Intel interfaces. When a bus mode other than eZ80 is programmed for a ...

  • Page 78

    Bit Position [3:0] BUS_CYCLE Notes: 1. Setting the BUS_CYCLE Intel Bus Mode causes the ALE pin to not function properly. 2. Use of the external WAIT input pin in Z80 Mode requires that BUS_CYCLE is set to ...

  • Page 79

    Watchdog Timer The Watchdog Timer (WDT) helps protect against corrupt or unreliable software, power faults, and other system-level problems which may place the eZ80 CPU into unsuitable operating states. The eZ80L92 MCU WDT features: • Four programmable time-out periods: 2 ...

  • Page 80

    Watchdog Timer Operation Enabling and Disabling the WDT The Watchdog Timer is disabled upon a system reset (RESET). To enable the WDT, the application program must set the WDT_EN bit (bit 7) of the WDT_CTL register. When enabled, the WDT ...

  • Page 81

    NMI event, provided that the last RESET was not caused by the WDT. Watchdog Timer Registers Watchdog Timer Control Register The Watchdog Timer Control register, described in ter used to enable the Watchdog Timer, set ...

  • Page 82

    Bit Position [1:0] WDT_PERIOD Note: *RST_FLAG is only cleared by a non-WDT RESET. Watchdog Timer Reset Register The Watchdog Timer Reset register, described in The Watchdog Timer is reset when an register. Any amount of time can occur between the ...

  • Page 83

    Programmable Reload Timers The eZ80L92 MCU features six Programmable Reload Timers (PRT). Each PRT contains a 16-bit downcounter and a 16-bit reload register. In addition, each PRT features a clock prescaler with four selectable taps for CLK ÷ 4, CLK ...

  • Page 84

    The time-out period of the PRT is returned by the following equation: PRT Time-Out Period To calculate the time-out period with the ...

  • Page 85

    Table 29. PRT SINGLE PASS Mode Operation Example Parameter PRT Enabled Reload and Restart Enabled PRT Clock Divider = 4 SINGLE PASS Mode PRT Interrupt Enabled PRT Reload Value CONTINUOUS Mode In CONTINUOUS mode, when the end-of-count value, automatically reloads ...

  • Page 86

    Table 30. PRT CONTINUOUS Mode Operation Example Parameter PRT Enabled Reload and Restart Enabled PRT Clock Divider = 4 CONTINUOUS Mode PRT Interrupt Enabled PRT Reload Value Reading the Current Count Value The CPU is capable of reading the current ...

  • Page 87

    Event Counter When Timers 0–3 are configured to take their inputs from port input pins PB0 and PB1, they function as event counters. For event counting, the clock prescaler is bypassed. The PRT counters decrement on every rising edge of ...

  • Page 88

    Table 31. PRT Timer Out Operation Example (Continued) Parameter PRT Clock Divider = 4 CONTINUOUS Mode PRT Reload Value Programmable Reload Timer Registers Each programmable reload timer is controlled using five 8-bit registers. These registers are the Timer Control register, ...

  • Page 89

    IRQ_EN 5 4 PRT_MODE [3:2] CLK_DIV 1 RST_EN 0 PRT_EN Timer Data Registers—Low Byte This Read-Only register returns the Low byte of the current count value of the selected timer. The Timer Data Register—Low Byte, detailed in timer is ...

  • Page 90

    Table 33. Timer Data Registers—Low Byte (TMR0_DR_L = 0081h, TMR1_DR_L = 0084h, TMR2_DR_L = 0087h, TMR3_DR_L = 008Ah, TMR4_DR_L = 008Dh, or TMR5_DR_L = 0090h) Bit Reset CPU Access Note Read only. Bit Position [7:0] TMRx_DR_L Timer Data ...

  • Page 91

    Bit Position [7:0] 00h–FFh These bits represent the High byte of the 2-byte timer data TMRx_DR_H Timer Reload Registers—Low Byte The Timer Reload Register—Low Byte, described in byte (LSB) of the 2-byte timer reload value. In CONTINUOUS mode, the timer ...

  • Page 92

    Timer Reload Registers—High Byte The Timer Reload Register—High Byte, detailed in byte (MSB) of the 2-byte timer reload value. In CONTINUOUS mode, the timer reload value is reloaded into the timer upon end-of-count. When RST_EN (TMRx_CTL[1]) is set to 1 ...

  • Page 93

    Table 37. Timer Input Source Select Register (TMR_ISS = 0092h) Bit Reset CPU Access Note: R/W = Read/Write. Bit Position [7:6] TMR3_IN [5:4] TMR2_IN [3:2] TMR1_IN [1:0] TMR0_IN PS013014-0107 R/W R/W R/W ...

  • Page 94

    Real Time Clock The real time clock (RTC) keeps time by maintaining a count of seconds, minutes, hours, day-of-the-week, day-of-the-month, year, and century. The current time is kept in 24-hour format. The format for all count and alarm registers is ...

  • Page 95

    Real Time Clock Alarm The clock can be programmed to generate an alarm condition when the current count matches the alarm set-point registers. Alarm registers are available for seconds, minutes, hours, and day-of-the-week. Each alarm can be independently enabled. To ...

  • Page 96

    Real Time Clock Registers The real time clock registers are accessed via the address and data bus using I/O instructions. RTC_UNLOCK controls access to the RTC count registers. When unlocked (RTC_UNLOCK = 1), the RTC count is disabled and the ...

  • Page 97

    Real Time Clock Minutes Register This register contains the current minutes count. See Table 39. Real Time Clock Minutes Register (RTC_MIN = 00E1h) Bit Reset CPU Access Note Unchanged by RESET; R/W* = Read-only if RTC locked, Read/Write ...

  • Page 98

    Real Time Clock Hours Register This register contains the current hours count. See Table 40. Real Time Clock Hours Register (RTC_HRS = 00E2h) Bit Reset CPU Access Note Unchanged by RESET; R/W* = Read-only if RTC locked, Read/Write ...

  • Page 99

    Real Time Clock Day-of-the-Week Register This register contains the current day-of-the-week count. The RTC_DOW register begins counting at 01h Table 41. Real Time Clock Day-of-the-Week Register (RTC_DOW = 00E3h) Bit Reset CPU Access Note Unchanged by RESET; R ...

  • Page 100

    Real Time Clock Day-of-the-Month Register This register contains the current day-of-the-month count. The RTC_DOM register begins counting at 01h Table 42. Real Time Clock Day-of-the-Month Register (RTC_DOM = 00E4h) Bit Reset CPU Access Note Unchanged by RESET; R/W* ...

  • Page 101

    Real Time Clock Month Register This register contains the current month count. See Table 43. Real Time Clock Month Register (RTC_MON = 00E5h) Bit Reset CPU Access Note Unchanged by RESET; R/W* = Read-only if RTC locked, Read/Write ...

  • Page 102

    Real Time Clock Year Register This register contains the current year count. See Table 44. Real Time Clock Year Register (RTC_YR = 00E6h) Bit Reset CPU Access Note Unchanged by RESET; R/W* = Read-only if RTC locked, Read/Write ...

  • Page 103

    Real Time Clock Century Register This register contains the current century count. See Table 45. Real Time Clock Century Register (RTC_CEN = 00E7h) Bit Reset CPU Access Note Unchanged by RESET; R/W* = Read-only if RTC locked, Read/Write ...

  • Page 104

    Real Time Clock Alarm Seconds Register This register contains the alarm seconds value. See Table 46. Real Time Clock Alarm Seconds Register (RTC_ASEC = 00E8h) Bit Reset CPU Access Note Unchanged by RESET; R/W = Read/Write. Binary-Coded-Decimal Operation ...

  • Page 105

    Real Time Clock Alarm Minutes Register This register contains the alarm minutes value. See Table 47. Real Time Clock Alarm Minutes Register (RTC_AMIN = 00E9h) Bit Reset CPU Access Note Unchanged by RESET; R/W = Read/Write. Binary-Coded-Decimal Operation ...

  • Page 106

    Real Time Clock Alarm Hours Register This register contains the alarm hours value. See Table 48. Real Time Clock Alarm Hours Register (RTC_AHRS = 00EAh) Bit Reset CPU Access Note Unchanged by RESET; R/W = Read/Write. Binary-Coded-Decimal Operation ...

  • Page 107

    Real Time Clock Alarm Day-of-the-Week Register This register contains the alarm day-of-the-week value. See Table 49. Real Time Clock Alarm Day-of-the-Week Register (RTC_ADOW = 00EBh) Bit Reset CPU Access Note Unchanged by RESET Read Only; R/W* ...

  • Page 108

    Real Time Clock Alarm Control Register This register contains alarm enable bits for the real-time clock. The RTC_ACTRL register is cleared by a RESET. See Table 50. Real Time Clock Alarm Control Register (RTC_ACTRL = 00ECh) Bit Reset CPU Access ...

  • Page 109

    CLK_SEL and FREQ_SEL select the RTC clock source. If the 32 kHz crystal option is selected the oscillator is enabled and the internal prescaler is set to divide by 32768. If the power-line frequency option is selected, the prescale value ...

  • Page 110

    Universal Asynchronous Receiver/ Transmitter The UART module implements the logic required to support various asynchronous communications protocols. The module also implements two separate 16-byte-deep FIFOs for both transmission and reception. A block diagram of the UART is illustrated in Figure ...

  • Page 111

    UART Functional Description The UART function implements the following: • The transmitter and associated control logic. • The receiver and associated control logic. • The modem interface and associated logic. UART Transmitter The transmitter block controls the data transmitted on ...

  • Page 112

    If the number of bits received is less than eight, the unused most significant bits of the data byte Read are 0. The receiver uses the clock ...

  • Page 113

    The third source of a receiver interrupt is a line status error, indicating an error in byte reception. This error may result from: • Incorrect received parity. • Incorrect framing; that is, the stop bit is not detected by receiver ...

  • Page 114

    Data Transfers—Transmit. rupt. An interrupt is immediately expected in response. The application reads the UARTx_IIR register and determines that the interrupt ...

  • Page 115

    UARTx_BRG_L) and outputs a pulse to indicate the end-of-count. Calculate the UART data rate with the following equation: UART Data Rate (bps) = Upon RESET, the 16-bit BRG divisor value resets to value of is also valid, and effectively bypasses ...

  • Page 116

    The UARTx_BRG_L registers share the same address space with the UARTx_RBR and Note: UARTx_THR registers. The UARTx_BRG_H registers share the same address space with the UARTx_IER registers. Bit 7 of the associated UART Line Control register (UARTx_LCTL) must be set ...

  • Page 117

    Write attributes, reset conditions, and bit descriptions of all of the UART registers are pro- vided in this section. UART Transmit Holding Registers If less than eight bits are programmed for transmission, the lower bits of the byte written to ...

  • Page 118

    Table 55. UART Receive Buffer Registers (UART0_RBR = 00C0h, UART1_RBR = 00 D0h) Bit Reset CPU Access Note Read only. Bit Position [7: UART Interrupt Enable Registers The UARTx_IER register is used to enable and ...

  • Page 119

    Bit Position 1 TIE 0 RIE UART Interrupt Identification Registers The Read-Only UARTx_IIR register allows you to check whether the FIFO is enabled and the status of interrupts. These registers share the same I/O addresses as the UARTx_FCTL registers. See ...

  • Page 120

    Table 58. UART Interrupt Status Codes INSTS Value 011 010 110 001 000 UART FIFO Control Registers This register is used to monitor trigger levels, clear FIFO pointers, and enable or disable the FIFO. The UARTx_FCTL registers share the same ...

  • Page 121

    Bit Position 2 CLRTXF 1 CLRRXF 0 FIFOEN UART Line Control Registers This register is used to control the communication control parameters. See Table 61. Table 60. UART Line Control Registers (UART0_LCTL = 00C3h, UART1_LCTL = 00D3h) Bit Reset CPU ...

  • Page 122

    Bit Position FPE 4 EPS 3 PEN [2:0] CHAR PS013014-0107 Value Description 0 Do not send a BREAK signal. 1 Send Break UART sends continuous zeroes on the transmit output from the next bit boundary. The transmit ...

  • Page 123

    Table 61. UART Character Parameter Definition CHAR[2:0] 000 001 010 011 100 101 110 111 UART Modem Control Registers This register is used to control and check the modem status. See Table 62. UART Modem Control Registers (UART0_MCTL = 00C4h, ...

  • Page 124

    Bit Position 3 OUT2 2 OUT1 1 RTS 0 DTR UART Line Status Registers This register is used to show the status of UART interrupts and registers. See Table 63. UART Line Status Registers (UART0_LSR = 00C5h, UART1_LSR = 00 ...

  • Page 125

    Bit Position 6 TEMT 5 THRE PS013014-0107 Value Description 0 Transmit holding register/FIFO is not empty or transmit shift register is not empty or transmitter is not idle. 1 Transmit holding register/FIFO and transmit ...

  • Page 126

    Bit Position UART Modem Status Registers This register is used to show the status of the UART signals. See Table 64. UART Modem Status Registers (UART0_MSR = 00C6h, UART1_MSR = 00 D6h) Bit Reset CPU Access ...

  • Page 127

    Bit Position 7 DCD DSR 4 CTS 3 DDCD 2 TERI 1 DDSR 0 DCTS PS013014-0107 Value Description 0–1 Data Carrier Detect In NORMAL mode, this bit reflects the inverted state of the DCDx input pin. In ...

  • Page 128

    UART Scratch Pad Registers The UARTx_SPR register can be used by the system as a general-purpose Read/Write register. See Table Table 65. UART Scratch Pad Registers (UART0_SPR = 00C7h, UART1_SPR = 00D7h) Bit Reset CPU Access Note: R/W = Read/Write. ...

  • Page 129

    Infrared Encoder/Decoder The eZ80L92 MCU contains a UART to infrared encoder/decoder (endec). The infrared encoder/decoder is integrated with the on-chip UART0 to allow easy communication between the eZ80 CPU and IrDA Physical Layer Specification Version 1.3 compliant infrared transceivers as ...

  • Page 130

    For more information on the UART and its Baud Rate Generator, see nous Receiver/Transmitter on page Transmit The data to be transmitted via the IR transceiver is first sent to UART0. The UART transmit signal (TxD) and Baud Rate Clock ...

  • Page 131

    High (1) period. Following the 3-clock Low pulse 6-clock High pulse to complete the full 16-clock data period. Data transmission is illustrated in Figure 26. 16-clock period Baud Rate Clock Start Bit = 0 ...

  • Page 132

    Table 66. GPIO Mode Selection while using the IrDA Encoder/Decoder Allowable GPIO GPIO Port D Bits Port Mode PD0 7 PD1 7 PD2–PD7 Any other than GPIO Mode 7 ( Loopback Testing ...

  • Page 133

    Bit Position 1 IR_RXEN 0 IR_EN PS013014-0107 Value Description 0 IR_RXD data is ignored. 1 IR_RXD data is passed to UART0 0 Infrared Encoder/Decoder is disabled. 1 Infrared Encoder/Decoder is enabled. Product Specification 127 Infrared Encoder/Decoder ...

  • Page 134

    Serial Peripheral Interface The Serial Peripheral Interface (SPI synchronous interface allowing several SPI-type devices to be interconnected. The SPI is a full-duplex, synchronous, and character- oriented communication channel that employs a four-wire interface. The SPI block con- sists ...

  • Page 135

    SPI Signals The four basic SPI signals are: • MISO (Master-In/Slave-Out) • MOSI (Master-Out/Slave-In) • SCK (SPI Serial Clock) • SS (Slave Select) The following section describes the SPI signals. Each signal is described in both MASTER and SLAVE modes. ...

  • Page 136

    Serial Clock The Serial Clock (SCK) is used to synchronize data movement both in and out of the device through its MOSI and MISO pins. The master and slave are capable of exchanging a data byte during a sequence of ...

  • Page 137

    SCK (CPOL bit = 0) SCK (CPOL bit = 1) Sample Input MSB (CPHA bit = 0) Data Out Sample Input (CPHA bit = 1) Data Out Enable (To Slave) Table 68. SPI Clock Phase and Clock Polarity Operation CPHA ...

  • Page 138

    The SPI is double-buffered on Read, but not on Write Write is performed during data transfer, the transfer occurs uninterrupted, and the Write is unsuccessful. This condition causes the WRITE COLLISION (WCOL) status bit in the SPI_SR register ...

  • Page 139

    Write Collision The WRITE COLLISION flag, WCOL (SPI_SR[5]), is set to 1 when an attempt is made to write to the SPI Transmit Shift register (SPI_TSR) while data transfer occurs. Clearing the WCOL bit is performed by reading SPI_SR with ...

  • Page 140

    When the SPI data transfer is complete, de-assert the ENABLE pin of the slave device. Data Transfer Procedure with SPI Configured as a Slave Follow the steps below for data transfer with SPI configured as the slave: 1. Load ...

  • Page 141

    Table 70. SPI Baud Rate Generator Register—High Byte (SPI_BRG_H = 00B9h) Bit Reset CPU Access Note: R/W = Read/Write. Bit Position [7:0] SPI_BRG_H SPI Control Register This register is used to control and setup the serial peripheral interface. The SPI ...

  • Page 142

    Bit Position 3 CPOL 2 CPHA [1:0] SPI Status Register The SPI Status Read-Only register returns the status of data transmitted using the serial peripheral interface. Reading the SPI_SR register clears Bits 7, 6, and logical 0. ...

  • Page 143

    SPI Transmit Shift Register The SPI Transmit Shift register (SPI_TSR) is used by the SPI master to transmit data onto the SPI serial bus to the slave device. A Write to the SPI_TSR register places data directly into the shift ...

  • Page 144

    Bit Position [7:0] RX_DATA PS013014-0107 Value Description 00h–FFh SPI received data. eZ80L92 MCU Product Specification 138 Serial Peripheral Interface ...

  • Page 145

    I C Serial I/O Interface General Characteristics 2 The I C serial I/O bus is a two-wire communication interface that can operate in four modes: • MASTER TRANSMIT • MASTER RECEIVE • SLAVE TRANSMIT • SLAVE RECEIVE 2 The ...

  • Page 146

    Data Validity The data on the SDA line must be stable during the High period of the clock. The High or Low state of the data line can only change when the clock signal on the SCL line is Low ...

  • Page 147

    Transferring Data Byte Format Every character transferred on the SDA line must be a single 8-bit byte. The number of bytes that can be transmitted per transfer is unrestricted. Each byte must be followed by an Acknowledge (ACK) Figure 32. ...

  • Page 148

    STOP or a repeated START condition. Data Output by Transmitter Data Output by Receiver SCL Signal from Master START Condition Clock Synchronization All masters generate their own ...

  • Page 149

    CLK1 Signal CLK2 Signal SCL Signal Arbitration A master may start a transfer only if the bus is free. Two or more masters may generate a START condition within the minimum hold time of the START condition which results in ...

  • Page 150

    A repeated START condition and a data bit. • A STOP condition and a data bit. • A repeated START condition and a STOP condition. Clock Synchronization for Handshake The Clock synchronizing mechanism can function as a handshake, enabling ...

  • Page 151

    Table 75 Master Transmit Status Codes 2 Code I C State 18h Addr+W transmitted ACK received 20h Addr+W transmitted, ACK not received 38h Arbitration lost 68h Arbitration lost, +W received, ACK transmitted 78h Arbitration lost, General call ...

  • Page 152

    Table 76 10-Bit Master Transmit Status Codes 2 Code I C State 38h Arbitration lost 68h Arbitration lost, SLA+W received, ACK transmitted B0h Arbitration lost, SLA+R received, ACK transmitted D0h Second Address byte + W transmitted, ACK ...

  • Page 153

    Table 77 Master Transmit Status Codes For Data Bytes (Continued State Code I 30h Data byte transmitted, ACK not received 38h Arbitration lost When all bytes are transmitted, the processor should write ...

  • Page 154

    Table 78 Master Receive Status Codes (Continued State Code I 48h Addr + R transmitted, ACK not received 38h Arbitration lost 68h Arbitration lost, SLA+W received, ACK transmitted 78h Arbitration lost, General call addr received, ...

  • Page 155

    Table 79 Master Receive Status Codes For Data Bytes 2 Code I C State 50h Data byte received, ACK transmitted 58h Data byte received, NACK transmitted 38h Arbitration lost in NACK bit When all bytes are received, ...

  • Page 156

    IFLG is set and the I2C_SR register contains the idle state. The AAK bit must be set to 1 before reentering SLAVE mode acknowledge is received after transmitting a byte, the IFLG is set and ...

  • Page 157

    I C Registers Addressing The processor interface provides access to six 8-bit registers: four Read/Write registers, one Read-Only register and two Write-Only registers, as indicated in 2 Table 80 Register Descriptions Register I2C_SAR I2C_XSAR I2C_DR I2C_CTL I2C_SR ...

  • Page 158

    Table 81. I2C Slave Address Register (I2C_SAR = 00C8h) Bit Reset CPU Access Note: R/W = Read/Write. Bit Position [7:1] SLA 0 GCE Extended Slave Address Register The I2C_XSAR register is used in conjunction with the I2C_SAR ...

  • Page 159

    Bit Position [7:0] SLAX Data Register This register contains the data byte/slave address to be transmitted or the data byte just received. In transmit mode, the most significant bit of the byte is transmitted first. In receive ...

  • Page 160

    SLAVE mode, the I enters MASTER mode when the bus is released. The STA bit is automatically cleared after a START condition is set. Writing this bit produces no effect. If the Master Mode Stop ...

  • Page 161

    Bit Position 7 IEN 6 ENAB 5 STA 4 STP 3 IFLG 2 AAK [1: Status Register The I2C_SR register is a Read-Only register that contains a 5-bit status code in the five most significant bits: the ...

  • Page 162

    There are 29 possible status codes, as listed in tains the status code ated and the IFLG bit in the I2C_CTL register is not set. All other status codes correspond to a defined state of the I When each of ...

  • Page 163

    Table 86 Status Codes (Continued) Code Status B0h Arbitration lost in address as master, slave address and Read bit received, ACK transmitted B8h Data byte transmitted in SLAVE mode, ACK received C0h Data byte transmitted in SLAVE ...

  • Page 164

    Bit Position [6:3] M [2: The I C clocks are derived from the eZ80L92’s system clock. The frequency of the eZ80L92 system clock supplied by: SAMP f SCLK f = SAMP MASTER ...

  • Page 165

    I C Software Reset Register The I2C_SRR register is a Write-Only register. Writing any value to this register performs a software reset of the I 2 Table 88 Software Reset Register (I2C_SRR = 00CDh) Bit Reset CPU ...

  • Page 166

    ... ZiLOG Debug Interface The ZiLOG Debug Interface (ZDI) provides a built-in debugging interface to the eZ80 CPU. ZDI provides basic in-circuit emulation features including: • Examining and modifying internal registers. • Examining and modifying memory. • Starting and stopping the user program. • ...

  • Page 167

    ... ZPAK emulator using a six-pin header. eZ80L92 MCU Figure 36. Schematic For Building a Target Board ZPAK Connector PS013014-0107 ZDI Clock Frequency 1 MHz 2 MHz 4 MHz 8 MHz 10 K‰ 10 K‰ TCK (ZCL) TDI (ZDA) 6-Pin Target Connector eZ80L92 MCU Product Specification 161 TV DD (Target ZiLOG Debug Interface ...

  • Page 168

    ... ZCL signal High. ZCL ZDA Start Signal PS013014-0107 Figure 37 Figure 38. When an operation is completed, the master stops during ZDI Data In ZDI Data In (Write) Figure 37. ZDI Write Timing eZ80L92 MCU Product Specification and Figure 38 illustrate a valid (Write) ZiLOG Debug Interface 162 ...

  • Page 169

    ... START command is issued at completion of the Read or Write operation, the operation PS013014-0107 ZDI Data Out (Read) Figure 38. ZDI Read Timing Bus Requests During ZDI Debug Mode returns the eZ80 Product ID Low Byte while a Write to this same 00h eZ80L92 MCU Product Specification 163 ZDI Data Out (Read) on page 167. ZiLOG Debug Interface ...

  • Page 170

    ... ZDI Address Byte msb Figure 39. ZDI Address Write Timing ZDI Data Byte msb of DATA eZ80L92 MCU Product Specification Single-Bit Byte Separator or new ZDI START Signal R/W 0/1 lsb 0 = WRITE 1 = READ lsb of DATA End of Data or New ZDI START Signal ZiLOG Debug Interface 164 ...

  • Page 171

    ... The most significant bit (msb) is shifted out first. for ZDI single-byte Read operations. PS013014-0107 Figure 41 illustrates the timing for ZDI Block ZDI Data Bytes msb of DATA of DATA Byte 1 Byte 1 eZ80L92 MCU Product Specification 0 lsb msb of DATA Byte 2 Single-Bit Byte Separator Figure 42 illustrates the timing ZiLOG Debug Interface 165 ...

  • Page 172

    ... Figure 43 illustrates the ZDI’s Block Read timing. ZDI Data Bytes msb of DATA of DATA Byte 1 Byte 1 eZ80L92 MCU Product Specification lsb of DATA End of Data or New ZDI START Signal ), the 20h 0 lsb msb of DATA Byte 2 Single-Bit Byte Separator ZiLOG Debug Interface 166 ...

  • Page 173

    ... To prevent data errors, ZDI should avoid data transmission while another device is controlling the bus. Finally, exiting ZDI Debug mode while an external peripheral controls the address and data buses, as indicated by BUSACK assertion, may produce unpredictable results. PS013014-0107 eZ80L92 MCU Product Specification 167 ZiLOG Debug Interface ...

  • Page 174

    ... Instruction Store 2 Instruction Store 1 Instruction Store 0 Write Memory register eZ80L92 MCU 168 Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh 00h 00h XXh XXh XXh 00h 00h XXh XXh XXh XXh XXh XXh ZiLOG Debug Interface ...

  • Page 175

    ... Read Memory Address Low Byte register Read Memory Address High Byte register Read Memory Address Upper Byte register Bus Status register Read Memory Data Value Table 92. eZ80L92 MCU Product Specification 169 Reset Value 06h 00h XXh 00h XXh XXh XXh 00h XXh ZiLOG Debug Interface ...

  • Page 176

    ... Note Write-only. PS013014-0107 Value Description 00h–FFh The four sets of ZDI address match registers are used for setting the addresses for generating break points. The 24-bit addresses are supplied by {ZDI_ADDRx_U, ZDI_ADDRx_H, ZDI_ADDRx_L, where Table 93 eZ80L92 MCU Product Specification ZiLOG Debug Interface 170 ...

  • Page 177

    ... The Ignore the Low Byte function of the ZDI Address Match 1 registers is enabled. If BRK_ADDR1 is set to 1, ZDI initiates a BREAK when only the upper 2 bytes of the 24-bit address, ADDR[23:8], match the 2-byte value {ZDI_ADDR1_U, ZDI_ADDR1_H result, a BREAK can occur anywhere within a 256-byte page. eZ80L92 MCU Product Specification 171 ZiLOG Debug Interface ...

  • Page 178

    ... ZDI SINGLE STEP mode is disabled. 1 ZDI SINGLE STEP mode is enabled. ZDI asserts a BREAK following execution of each instruction Value Description 0 No action. 1 Initiate a RESET of the eZ80L92. This bit is automatically cleared at the end of the RESET event. 0000000 Reserved. eZ80L92 MCU Product Specification ZiLOG Debug Interface 172 ...

  • Page 179

    ... ZDI_WR_H, ZDI_WR_L}. If less than 24 bits of data are required to complete the required operation, the data is taken from the least significant byte(s). Table 96. Table 96. For more information on the ® CPU User Manual (UM0077). eZ80L92 MCU Product Specification 16h ZiLOG Debug Interface 173 ...

  • Page 180

    ... IXU ZDI_WR_U ← IXH ZDI_WR_H ← IXL ZDI_WR_L Write IY ← IYU ZDI_WR_U ← IYH ZDI_WR_H ← IYL ZDI_WR_L Write SP In ADL mode SPL. In Z80 mode SPS. Write PC ← PC[23:16] ZDI_WR_U ← PC[15:8] ZDI_WR_H ← PC[7:0] ZDI_WR_L Reserved ZiLOG Debug Interface 174 ...

  • Page 181

    ... AF’ ← BC’ ← DE’ ← HL’ 8B ’s alternate register set (A’, F’, B’, C’, D’, E’, HL’) cannot be read directly. register set. 97 eZ80L92 MCU Product Specification (Continued) Command Reserved Reserved Write memory from current PC value, increment ZiLOG Debug Interface 175 0 0 ...

  • Page 182

    ... Deassert the bus acknowledge pin (BUSACK) to return control of the address and data buses back to ZDI. 1 Assert the bus acknowledge pin (BUSACK) to pass control of the address and data buses to an external peripheral. 000000 Reserved. eZ80L92 MCU Product Specification 176 Table 98. Instruc- ZiLOG Debug Interface ...

  • Page 183

    ... CPU following a Write to ZDI_IS0. The ZDI_IS0 register contains the first Op Code of the instruction. The remaining ZDI_ISx registers contain any additional Op Codes or operand dates required for execution of the required instruction eZ80L92 MCU Product Specification Table 99 ZiLOG Debug Interface 177 ...

  • Page 184

    ... Product ID Low Byte Register (ZDI_ID_L = 00h in the ZDI Value Description 06h {ZDI_ID_H, ZDI_ID_L} = {00h, 06h} indicates the eZ80L92 product. ® Product ID High Byte Register (ZDI_ID_H = 01h in the ZDI eZ80L92 MCU Product Specification ← 8 bits See 00h 06h ZiLOG Debug Interface 178 ← ...

  • Page 185

    ... Note Read-only. PS013014-0107 Value Description 00h {ZDI_ID_H, ZDI_ID_L} = {00h, 06h} indicates the eZ80L92 product. 102. ® Product ID Revision Register (ZDI_ID_REV = 02h in the ZDI Value Description 00h–FFh Identifies the current revision of the eZ80L92 product eZ80L92 MCU Product Specification ZiLOG Debug Interface 179 ...

  • Page 186

    ... The CPU’s Mixed-Memory mode (MADL) bit is set The CPU’s Interrupt Enable Flag 1 is reset to 0. Maskable interrupts are disabled. 1 The CPU’s Interrupt Enable Flag 1 is set to 1. Maskable interrupts are enabled. 00 Reserved eZ80L92 MCU Product Specification 180 Table 104 ZiLOG Debug Interface ...

  • Page 187

    ... Address and data buses are not relinquished to an external peripheral. bus acknowledge is deasserted (BUSACK pin is High). 1 Address and data buses are relinquished to an external peripheral. bus acknowledge is asserted (BUSACK pin is Low). 000000 Reserved. eZ80L92 MCU Product Specification 181 Table 105 ZiLOG Debug Interface ...

  • Page 188

    ... CPU’s program counter. In Z80 MEMORY mode, 8-bit data is transferred out from address {MBASE, PC[15:0]}. In ADL Memory mode, 8-bit data is transferred out from address PC[23:0]. eZ80L92 MCU Product Specification 182 fetches the eZ80L92 ZiLOG Debug Interface ...

  • Page 189

    ... On-Chip Instrumentation debugging features. The OCI provides run control, memory and register visibility, com- plex breakpoints, and trace history features. The OCI employs all the functions of the ZiLOG Debug Interface (ZDI) as described in the ZDI section. It also adds the following debug features: • ...

  • Page 190

    OCI Interface There are five dedicated pins on the eZ80L92 MCU for the OCI interface. Four pins (TCK, TMS, TDI, and TDO) are required for IEEE Standard 1149.1-compatible JTAG ports. The TRIGOUT pin provides additional testability features. OCI pins . ...

  • Page 191

    OCI Information Requests For additional information regarding On-Chip Instrumentation order OCI debug tools, please contact: First Silicon Solutions, Inc. 5440 SW Westgate Drive, Suite 240 Portland, OR 97221 Phone: (503) 292-6730 Fax: (503) 292-5840 www.fs2.com PS013014-0107 eZ80L92 MCU ...

  • Page 192

    CPU Instruction Set Table 108 through eZ80L92 MCU. The instructions are grouped by class. A detailed information is available in the eZ80 CPU User Manual. Table 108. Arithmetic Instructions Mnemonic ADC ADD CP DAA DEC INC MLT NEG ...

  • Page 193

    Table 108. Block Transfer and Compare Instructions Mnemonic LDD (LDDR) LDI (LDIR) Table 108. Exchange Instructions Mnemonic EX EXX Table 108. Input/Output Instructions Mnemonic IN IN0 IND (INDR) INDRX IND2 (IND2R) INDM (INDMR) INI (INIR) INIRX INI2 (INI2R) INIM (INIMR) ...

  • Page 194

    Table 108. Input/Output Instructions Mnemonic OUT0 OUTD (OTDR) OUTD2 (OTD2R) OUTI (OTIR) OUTI2 (OTI2R) TSTIO Table 108. Load Instructions Mnemonic LD LEA PEA POP PUSH Table 108. Logical Instructions Mnemonic AND CPL OR TST XOR Table 108. Processor Control Instructions ...

  • Page 195

    Table 108. Processor Control Instructions Mnemonic EI HALT IM NOP RSMIX SCF SLP STMIX Table 108. Program Control Instructions Mnemonic CALL CALL cc DJNZ RET RET cc RETI RETN RST Table 108. Rotate and ...

  • Page 196

    Table 108. Rotate and Shift Instructions Mnemonic RLC RLCA RLD RR RRA RRC RRCA RRD SLA SRA SRL PS013014-0107 Instruction Rotate Left Circular Rotate Left Circular–Accumulator Rotate Left Decimal Rotate Right Rotate Right–Accumulator Rotate Right Circular Rotate Right Circular–Accumulator Rotate ...

  • Page 197

    Opcode Map Table 109 through Table 109. Opcode Map—First Opcode Legend Lower opcode Nibble Upper opcode 4 Nibble AND Mnemonic A A,H First Operand Second Operand INC INC 0 NOP BC, (BC),A BC Mmn ...

  • Page 198

    Table 110. Opcode Map—Second Opcode after 0CBh Legend Lower Nibble of 2nd cpcode Upper Nibble 4 of Second RES Mnemonic cpcode A 4,H First Operand Second Operand RLC RLC RLC RLC RLC ...

  • Page 199

    Table 111. Opcode Map—Second Opcode After 0DDh Legend Lower Nibble of 2nd opcode Upper 9 Nibble of Second LD Mnemonic F opcode SP,IX Second Operand First Operand INC 2 IX, (Mmn), IX ...

  • Page 200

    Table 112. Opcode Map—Second Opcode After 0EDh Legend Lower Nibble of 2nd opcode Upper 2 Nibble of Second SBC Mnemonic 4 opcode HL,BC First Operand Second Operand IN0 OUT0 LEA BC, LEA BC, TST 0 B,(n) ...