EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 113

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
UART Recommended Usage
The third source of a receiver interrupt is a line status error, indicating an error in byte
reception. This error may result from:
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•
•
•
An interrupt due to one of the above conditions is cleared when the UARTx_LSR register
is read. In FIFO mode, a line status interrupt is generated only after the received byte with
an error reaches the top of the FIFO and is ready to be read.
A line status interrupt is activated (provided this interrupt is enabled) as long as the Read
pointer of the receiver FIFO points to the location of the FIFO that contains a byte with the
error. The interrupt is immediately cleared when the UARTx_LSR register is read. The
ERR bit of the UARTx_LSR register is active as long as an erroneous byte is present in the
receiver FIFO.
UART Modem Status Interrupt
The modem status interrupt is generated if there is any change in state of the modem status
inputs to the UART. This interrupt is cleared when the processor reads the UARTx_MSR
register.
The following is the standard sequence of events that occur in the eZ80L92 MCU using
the UART. A description of each follows.
1. Module reset.
2. Control transfers to configure UART operation.
3. Data transfers.
Module Reset.
mand status registers are programmed with their default values, and the FIFOs are flushed.
Control Transfers.
rate is determined and the BRG is configured to generate a 16X clock frequency. Inter-
rupts are disabled and the communication control parameters are programmed in the
UARTx_LCTL register. The FIFO configuration is determined and the receive trigger lev-
els are set in the UARTx_FCTL register. The status registers, UARTx_LSR and
UARTx_MSR, are read, and ensure that none of the interrupt sources are active. The inter-
Incorrect received parity.
Incorrect framing; that is, the stop bit is not detected by receiver at the end of the byte.
Receiver over run condition.
A BREAK condition being detected on the receive data input.
Upon reset, all internal registers are set to their default values. All com-
Based on the requirements of the application, the data transfer baud
Universal Asynchronous Receiver/Transmitter
Product Specification
eZ80L92 MCU
107