EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 118

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
Table 55. UART Receive Buffer Registers (UART0_RBR = 00C0h, UART1_RBR =
UART Interrupt Enable Registers
The UARTx_IER register is used to enable and disable the UART interrupts. The
UARTx_IER registers share the same I/O addresses as the UARTx_BRG_H registers. See
Table
Table 56. UART Interrupt Enable Registers (UART0_IER = 00C1h, UART1_IER =
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
[7:0]
R
Bit
Reset
CPU Access
Note: R = Read only.; R/W = Read/Write.
Bit
Position
[7:4]
3
MIIE
2
LSIE
x
D
56.
00D1h)
00 D0h)
00h–FFh Receive data byte.
Value Description
0000
Value
0
1
0
1
Reserved
Modem interrupt on edge detect of status inputs is disabled.
Modem interrupt on edge detect of status inputs is enabled.
Line status interrupt is disabled.
Line status interrupt is enabled for receive data errors:
incorrect parity bit received, framing error, overrun error, or
break detection.
X
R
R
7
7
0
Description
X
R
R
6
6
0
R
R
X
5
5
0
Universal Asynchronous Receiver/Transmitter
R
R
X
4
4
0
R/W
R
X
3
3
0
Product Specification
R/W
R
X
2
2
0
eZ80L92 MCU
R/W
X
R
1
1
0
R/W
X
R
0
0
0
112