EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 121

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
UART Line Control Registers
This register is used to control the communication control parameters. See
Table
Table 60. UART Line Control Registers (UART0_LCTL = 00C3h, UART1_LCTL =
Bit
Position
2
CLRTXF
1
CLRRXF
0
FIFOEN
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
7
DLAB
61.
00D3h)
Value Description
Value Description
0
1
0
1
0
1
0
1
No effect.
Clear the transmit FIFO and reset the transmit FIFO pointer.
Valid only if the FIFO is enabled.
No effect.
Clear the receive FIFO, clear the receive error FIFO, and reset
the receive FIFO pointer. Valid only if the FIFO is enabled.
Transmit and receive FIFOs are disabled. Transmit and receive
buffers are only 1 byte deep.
Transmit and receive FIFOs are enabled.
R/W
Access to the UART registers at I/O addresses UARTx_RBR,
UARTx_THR, and UARTx_IER is enabled.
Access to the Baud Rate Generator registers at I/O addresses
UARTx_BRG_L and UARTx_BRG_H is enabled.
7
0
R/W
6
0
R/W
5
0
Universal Asynchronous Receiver/Transmitter
R/W
4
0
R/W
3
0
Product Specification
R/W
2
0
eZ80L92 MCU
Table 60
R/W
1
0
R/W
and
0
0
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