EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 156

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
Note:
is transmitted, the IFLG is set and the I2C_SR register contains
the idle state. The AAK bit must be set to 1 before reentering SLAVE mode.
If no acknowledge is received after transmitting a byte, the IFLG is set and the I2C_SR
register contains
If a STOP condition is detected after an acknowledge bit, the I
Slave Receive
In SLAVE RECEIVE mode, a number of data bytes are received from a master transmit-
ter.
The I
Write bit (lsb = 0) after a START condition. The I
the IFLG bit in the I2C_CTL register and the I2C_SR register contains the status code
60h
address
When the I
ister), it transmits an acknowledge after the first address byte is received but no interrupt is
generated. IFLG is not set and the status does not change. The I
only after the second address byte is received. The I
tus code as described above.
I
the transmission of an address, and the slave address and Write bit (or the general call
address if the CGE bit in the I2C_SAR register is set to 1) are received. The status code in
the I2C_SR register is
address is received. The IFLG bit must be cleared to 0 to allow data transfer to continue.
If the AAK bit in the I2C_CTL register is set to 1 then an acknowledge bit (Low level on
SDA) is transmitted and the IFLG bit is set after each byte is received. The I2C_SR regis-
ter contains the status code
general call address. The received data byte can be read from the I2C_DR register and the
IFLG bit must be cleared to allow the transfer to continue. If a STOP condition or a
repeated START condition is detected after the acknowledge bit, the IFLG bit is set and
the I2C_SR register contains status code
If the AAK bit is cleared to 0 during a transfer, the I
(High level on SDA) after the next byte is received, and set the IFLG bit. The I2C_SR reg-
ister contains the status code
general call address. The I
2
C goes from MASTER mode to SLAVE RECEIVE mode when arbitration is lost during
. The I
2
C enters SLAVE RECEIVE mode when it receives its own slave address and a
00h
2
2
C also enters SLAVE RECEIVE mode when it receives the general call
C contains a 10-bit slave address (signified by
(if the GCE bit in the I2C_SAR register is set). The status code is then
C0h
. The I
68h
2
C returns to the idle state when the IFLG bit is cleared to 0.
if the slave address is received or
80h
2
C then returns to the idle state.
88h
or
or
90h
98h
if SLAVE RECEIVE mode is entered with the
A0h
if SLAVE RECEIVE mode is entered with the
.
2
C transmits an acknowledge bit and sets
2
2
C sets the IFLG bit and loads the sta-
C transmits a not-acknowledge bit
F0h–F7h
78h
2
C returns to the idle state.
C8h
2
Product Specification
C generates an interrupt
if the general call
and the I
in the I2C_SAR reg-
I
2
C Serial I/O Interface
2
C returns to
70h
.
150