EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 157

IC WEBSERVER 50MHZ 100LQFP

EZ80L92AZ050SG

Manufacturer Part Number
EZ80L92AZ050SG
Description
IC WEBSERVER 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet

Specifications of EZ80L92AZ050SG

Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3878
EZ80L92AZ050SG

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Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80L92AZ050SG
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Part Number:
EZ80L92AZ050SG
Manufacturer:
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Quantity:
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PS013014-0107
I
2
C Registers
Addressing
The processor interface provides access to six 8-bit registers: four Read/Write registers,
one Read-Only register and two Write-Only registers, as indicated in
Table 80. I
Resetting the I
Hardware reset.
I2C_XSAR, I2C_DR and I2C_CTL registers are cleared to
ter is set to
Software Reset.
Register (I2C_SRR). A software reset sets the I
IFLG bits of the I2C_CTL register to 0.
I
The I2C_SAR register provides the 7-bit address of the I
allows 10-bit addressing in conjunction with the I2C_XSAR register. I2C_SAR[7:1] =
sla[6:0] is the 7-bit address of the I
this address after a START condition, it enters SLAVE mode. I2C_SAR[7] corresponds to
the first bit received from the I
When the register receives an address starting with
the I
ACK after receiving the I2C_SAR byte (the device does not generate an interrupt at this
point). After the next byte of the address (I2C_XSAR) is received, the I
interrupt and goes into SLAVE mode. Then I2C_SAR[2:1] are used as the upper 2 bits for
the 10-bit extended address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}. See
Register
I2C_SAR
I2C_XSAR
I2C_DR
I2C_CTL
I2C_SR
I2C_CCR
I2C_SRR
2
C Slave Address Register
2
C recognizes that a 10-bit slave addressing mode is being selected. The I
F8h
2
C Register Descriptions
.
2
When the I
Perform a software reset by writing any value to the I
C Registers
Extended slave address register
Data byte register
Control register
Status register (Read-Only)
Clock Control register (Write-Only)
Software reset register (Write-Only)
Description
Slave address register
Table
2
81.
C is reset by a hardware reset of the eZ80L92, the I2C_SAR,
2
C bus.
2
C when in 7-bit SLAVE mode. When the I
2
C back to idle and the STP, STA, and
F7h
to
2
C when in SLAVE mode and
F0h
00h
(I2C_SAR[7:3] = 11110b),
; while the I2C_SR regis-
Product Specification
Table
I
2
2
C Serial I/O Interface
2
C Software Reset
C generates an
80.
2
2
C sends an
C receives
151

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