EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 159

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
I
This register contains the data byte/slave address to be transmitted or the data byte just
received. In transmit mode, the most significant bit of the byte is transmitted first. In
receive mode, the first bit received is placed in the most significant bit of the register.
After each byte is transmitted, the I2C_DR register contains the byte that is present on the
bus in case a lost arbitration event occurs. See
Table 83. I
I
The I2C_CTL register is a control register that is used to control the interrupts and the
master slave relationships on the I
When the Interrupt Enable bit (IEN) is set to 1, the interrupt line goes High when the IFLG
is set to 1. When IEN is cleared to 0, the interrupt line always remains Low.
When the Bus Enable bit (ENAB) is set to 0, the I
ignored and the I
set to 1, the I
GCE bit (I2C_SAR[0]) is set to 1.
When the Master Mode Start bit (STA) is set to 1, the I
sends a START condition on the bus when the bus is free. If the STA bit is set to 1 when
the I
repeated START condition is sent. If the STA bit is set to 1 when the I
Bit
Position
[7:0]
SLAX
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
DATA
2
2
C Data Register
C Control Register
2
C module is already in MASTER mode and one or more bytes are transmitted, then a
2
C Data Register
2
C responds to calls to its slave address and to the general call address if the
2
00h–FFh Least significant 8 bits of the 10-bit extended slave address.
C module does not respond to any address on the bus. When ENAB is
Value
00h–FFh
Value
R/W
Description
7
0
(I2C_DR = 00CAh)
Description
I
2
2
R/W
C data byte.
C bus.
6
0
R/W
5
0
Table
2
R/W
C bus inputs SCLx and SDAx are
4
0
83.
2
C enters MASTER mode and
R/W
3
0
Product Specification
R/W
2
0
I
2
2
C block is being
C Serial I/O Interface
R/W
1
0
R/W
0
0
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