EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 213

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

Table 122. External Write Timing
PS013014-0107
Parameter
T
T
T
T
T
T
T
T
T
T
Note: *At the conclusion of a Write cycle, de-assertion of WR always occurs before any change to ADDR, DATA, CSx,
1
2
3
4
5
6
7
8
9
10
or MREQ. In certain applications, the de-assertion of WR can be concurrent with ADDR, DATA, CSx, or MREQ
when buffering is used off-chip.
Description
Clock Rise to ADDR Valid Delay
Clock Rise to ADDR Hold Time
Clock Fall to Output DATA Valid Delay
DATA Hold Time from Clock Rise
Clock Rise to CSx Assertion Delay
Clock Rise to CSx Deassertion Delay
Clock Rise to MREQ Assertion Delay
Clock Rise to MREQ Deassertion Delay
Clock Fall to WR Assertion Delay
Clock Rise to WR Deassertion Delay*
Min
2.4
3.2
2.9
2.8
2.6
1.5
1.4
2.4
—
—
20 MHz (ns)
Max
10.2
10.3
9.7
9.6
6.9
5.0
3.6
—
—
6
Product Specification
Min
2.4
2.4
3.2
2.9
2.8
2.6
1.5
1.4
—
—
50 MHz (ns)
AC Characteristics
Max
10.2
10.3
9.7
9.6
6.9
5.0
3.6
—
—
6
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