EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 45

IC WEBSERVER 50MHZ 100LQFP

EZ80L92AZ050SG

Manufacturer Part Number
EZ80L92AZ050SG
Description
IC WEBSERVER 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet

Specifications of EZ80L92AZ050SG

Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3878
EZ80L92AZ050SG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80L92AZ050SG
Manufacturer:
Everlight
Quantity:
12 000
Part Number:
EZ80L92AZ050SG
Manufacturer:
Zilog
Quantity:
10 000
Table 6. GPIO Mode Selection
PS013014-0107
GPIO
Mode
1
2
3
4
5
6
7
8
9
Px_ALT2
Bits7:0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
GPIO Mode 1.
written to the Port x Data register (Px_DR) is located on the pin.
GPIO Mode 2.
tristated (high impedance). The value stored in the Port x Data register produces no effect.
As in all modes, a Read from the Port x Data register returns the pin’s value. GPIO Mode
2 is the default operating mode following a RESET.
GPIO Mode 3.
an internal pull-up to the supply voltage. To employ the GPIO pin in OPEN-DRAIN
mode, an external pull-up resistor must connect the pin to the supply voltage. Writing a 0
to the Port x Data register outputs a Low at the pin. Writing a 1 to the Port x Data register
results in high-impedance output.
GPIO Mode 4.
feature an internal pull-down to the supply ground. To employ the GPIO pin in OPEN-
SOURCE mode, an external pull-down resistor must connect the pin to the supply ground.
Px_ALT1
Bits7:0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
This port pin is configured as a standard digital output pin. The value
The port pin is configured as a standard digital input pin. The output is
The port pin is configured as open-drain I/O. The GPIO pins do not feature
The port pin is configured as open-source I/O. The GPIO pins do not
Px_DDR
Bits7:0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bits7:0 Port Mode
Px_DR
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output
Output
Input from pin
Input from pin
Open-Drain output
Open-Drain I/O
Open source I/O
Open source output
Reserved
Interrupt—dual edge triggered
Port B, C, or D—alternate function controls port I/O.
Port B, C, or D—alternate function controls port I/O.
Interrupt—active Low
Interrupt—active High
Interrupt—falling edge triggered
Interrupt—rising edge triggered
General-Purpose Input/Output
Product Specification
1
Output
0
1
High impedance
High impedance
0
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
eZ80L92 MCU
39

Related parts for EZ80L92AZ050SG